Datasheet

ISO1050
SLLS983H –JUNE 2009–REVISED JUNE 2013 www.ti.com
DEVICE SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Total loop delay, driver input to receiver output, Recessive to
t
loop1
See Figure 12 112 150 210 ns
Dominant
Total loop delay, driver input to receiver output, Dominant to
t
loop2
See Figure 12 112 150 210 ns
Recessive
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CANH 2.9 3.5 4.5
V
O(D)
Bus output voltage (Dominant) See Figure 4 and Figure 5, V
I
= 0 V, R
L
= 60Ω V
CANL 0.8 1.2 1.5
V
O(R)
Bus output voltage (Recessive) See Figure 4 and Figure 5, V
I
= 2 V, R
L
= 60Ω 2 2.3 3 V
See Figure 4, Figure 5 and Figure 6, V
I
= 0 V,
1.5 3
R
L
= 60Ω
V
OD(D)
Differential output voltage (Dominant) V
See Figure 4, Figure 5, and Figure 6 V
I
= 0 V,
1.4 3
R
L
= 45Ω, Vcc > 4.8V
See Figure 4 and Figure 5, V
I
= 3 V, R
L
= 60Ω –0.12 0.012
V
OD(R)
Differential output voltage (Recessive) V
V
I
= 3 V, No Load –0.5 0.05
V
OC(D)
Common-mode output voltage (Dominant) 2 2.3 3
See Figure 11 V
V
OC(pp)
Peak-to-peak common-mode output voltage 0.3
I
IH
High-level input current, TXD input V
I
at 2 V 5 μA
I
IL
Low-level input current, TXD input V
I
at 0.8 V –5 μA
I
O(off)
Power-off TXD leakage current V
CC1
, V
CC2
at 0 V, TXD at 5 V 10 μA
See Figure 14, V
CANH
= –12 V, CANL Open –105 –72
See Figure 14, V
CANH
= 12 V, CANL Open 0.36 1
I
OS(ss)
Short-circuit steady-state output current mA
See Figure 14, V
CANL
=–12 V, CANH Open –1 –0.5
See Figure 14, V
CANL
= 12 V, CANH Open 71 105
C
O
Output capacitance See receiver input capacitance
CMTI Common-mode transient immunity See Figure 16, V
I
= V
CC
or 0 V 25 50 kV/μs
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, recessive-to-dominant output 31 74 110
t
PHL
Propagation delay time, dominant-to-recessive output 25 44 75
See Figure 7 ns
t
r
Differential output signal rise time 20 50
t
f
Differential output signal fall time 20 50
t
dom
(1)
Dominant time-out ↓ C
L
=100 pF, See Figure 13 300 450 700 μs
(1) The TXD dominant time out (t
dom
) disables the driver of the transceiver once the TXD has been dominant longer than (t
dom
) which
releases the bus lines to recessive preventing a local failure from locking the bus dominant. The driver may only transmit dominant
again after TXD has been returned HIGH (recessive). While this protects the bus from local faults locking the bus dominant it limits the
minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case
where five successive dominant bits are followed immediately by an error frame. This along with the (t
dom
) minimum limits the minimum
bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ (t
dom
) = 11 bits / 300 µs = 37 kbps.
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