Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- FUNCTIONAL DESCRIPTION
- PROTECTION FEATURES
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- SUPPLY CURRENT
- DEVICE SWITCHING CHARACTERISTICS
- DRIVER ELECTRICAL CHARACTERISTICS
- DRIVER SWITCHING CHARACTERISTICS
- RECEIVER ELECTRICAL CHARACTERISTICS
- RECEIVER SWITCHING CHARACTERISTICS
- PARAMETER MEASUREMENT INFORMATION
- DEVICE INFORMATION
- ISOLATOR CHARACTERISTICS
- INSULATION CHARACTERISTICSISO1050LDW from INSULATION CHARACTERISTICS
- IEC 60664-1 RATINGS
- IEC SAFETY LIMITING VALUES
- REGULATORY INFORMATIONISO1050LDW from REGULATORY INFORMATION
- THERMAL INFORMATION (DUB-8 PACKAGE)
- THERMAL INFORMATION (DW-16 PACKAGE)
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- REVISION HISTORY

ISO1050
SLLS983H –JUNE 2009–REVISED JUNE 2013
www.ti.com
CAN Bus Short Circuit Current Limiting
The device has several protection features that limit the short circuit current when a CAN bus line is shorted.
These include driver current limiting (dominant and recessive). The device has TXD dominant state time out to
prevent permanent higher short circuit current of the dominant state during a system fault. During CAN
communication the bus switches between dominant and recessive states with the data and control fields bits,
thus the short circuit current may be viewed either as the instantaneous current during each bus state, or as a
DC average current. For system current (power supply) and power considerations in the termination resistors
and common-mode choke ratings, use the average short circuit current. Determine the ratio of dominant and
recessive bits by the data in the CAN frame plus the following factors of the protocol and PHY that force either
recessive or dominant at certain times:
• Control fields with set bits
• Bit stuffing
• Interframe space
• TXD dominant time out (fault case limiting)
These ensure a minimum recessive amount of time on the bus even if the data field contains a high percentage
of dominant bits.
NOTE
The short circuit current of the bus depends on the ratio of recessive to dominant bits and
their respective short circuit currents. The average short circuit current may be calculated
with the following formula:
I
OS(AVG)
= %Transmit × [(%REC_Bits × I
OS(SS)_REC
) + (%DOM_Bits × I
OS(SS)_DOM
)] +
[%Receive × I
OS(SS)_REC
]
Where
• I
OS(AVG)
is the average short circuit current
• %Transmit is the percentage the node is transmitting CAN messages
• %Receive is the percentage the node is receiving CAN messages
• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages
• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
• I
OS(SS)_REC
is the recessive steady state short circuit current
• I
OS(SS)_DOM
is the dominant steady state short circuit current
NOTE
Consider the short circuit current and possible fault cases of the network when sizing the
power ratings of the termination resistance and other network components.
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