Datasheet

(e +
NI
2
´
e
NO
2
G
´
6
V
DIFF
BW
INA827
SBOS631A –JUNE 2012–REVISED JULY 2013 www.ti.com
Resistor-adjustable INAs such as the INA827 yield the lowest gain error at G = 5 because of the inherently well-
matched drift of the internal resistors of the differential amplifier. At gains greater than 5 (for instance, G = 10 V/V
or G = 100 V/V) gain error becomes a significant error source because of the resistor drift contribution of the
feedback resistors in conjunction with the external gain resistor. Except for very high gain applications, gain drift
is by far the largest error contributor compared to other drift errors (such as offset drift). The INA827 offers the
lowest gain error over temperature in the marketplace for both G > 5 and G = 5 (no external gain resistor).
Table 2 summarizes the major error sources in common INA applications and compares the two cases of G = 5
(no external resistor) and G = 10 (with a 16-kΩ external resistor). As can be seen in Table 2, while the static
errors (absolute accuracy errors) in G = 5 are almost twice as great as compared to G = 10, there is a great
reduction in drift errors because of the significantly lower gain error drift. In most applications, these static errors
can readily be removed during calibration in production. All calculations refer the error to the input for easy
comparison and system evaluation.
Table 2. Error Calculation
INA827
G = 10 ERROR G = 1 ERROR
SPECIFICATION
ERROR SOURCE ERROR CALCULATION (ppm) (ppm)
ABSOLUTE ACCURACY AT +25°C
Input offset voltage (µV) V
OSI
/ V
DIFF
150 150 150
Output offset voltage (µV) V
OSO
/ (G × V
DIFF
) 2000 200 400
Input offset current (nA) I
OS
× maximum (R
S+
, R
S–
) / V
DIFF
5 50 50
94 (G = 10),
CMRR (dB) 200 398
V
CM
/ (10
CMRR / 20
× V
DIFF
)
88 (G = 5)
Total absolute accuracy error (ppm) 600 998
DRIFT TO +105°C
25 (G = 10),
Gain drift (ppm/°C) GTC × (T
A
– 25) 2000 80
1 (G = 5)
Input offset voltage drift (μV/°C) (V
OSI_TC
/ V
DIFF
) × (T
A
– 25) 5 200 200
Output offset voltage drift (μV/°C) [V
OSO_TC
/ ( G × V
DIFF
)] × (T
A
– 25) 30 240 240
Total drift error (ppm) 2440 760
RESOLUTION
Gain nonlinearity (ppm of FS) 5 5 5
e
NI
= 17
Voltage noise (1 kHz) 6 6
e
NO
= 250
Total resolution error (ppm) 11 11
TOTAL ERROR
Total error Total error = sum of all error sources 3051 1769
LAYOUT GUIDELINES
Attention to good layout practices is always recommended. Keep traces short and, when possible, use a printed
circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as possible.
Place 0.1-μF bypass capacitors close to the supply pins. These guidelines should be applied throughout the
analog circuit to improve performance and provide benefits such as reducing the electromagnetic-interference
(EMI) susceptibility.
CMRR vs Frequency
The INA827 pinout has been optimized for achieving maximum CMRR performance over a wide range of
frequencies. However, care must be taken to ensure that both input paths are well-matched for source
impedance and capacitance to avoid converting common-mode signals into differential signals. In addition,
parasitic capacitance at the gain-setting pins can also affect CMRR over frequency. For example, in applications
that implement gain switching using switches or PhotoMOS
®
relays to change the value of R
G
, the component
should be chosen so that the switch capacitance is as small as possible.
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