Datasheet

1 19 9
1 0 0 0 0 0 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0
Frame 1: Two-Wire Slave Address Byte
(1)
Frame 2: Register Pointer Byte
Start By
Master
ACK By
Device
ACK By
Device
Stop By
Master
SCL
SDA
1 9
1 0 0 0 0 0 A0
Frame 1: SMBus ALERT Response
Address Byte
Frame 2: Slave Address Byte
(1)
Start By
Master
ACK By
Device
Stop By
Master
No ACK By
Master
(2)
From
Device
1
10 0 0 0
R/W
SCL
SDA
1 0
9
0
INA3221
www.ti.com SBOS576A –MAY 2012–REVISED JUNE 2013
Figure 31 shows the timing diagram for the SMBus Alert response operation. Figure 32 illustrates a typical
register pointer configuration.
(1) The value of the Slave Address Byte is determined by the A0 pin setting. Refer to Table 7.
Figure 31. Timing Diagram for SMBus ALERT
(1) The value of the Slave Address Byte is determined by the A0 pin setting. Refer to Table 7.
Figure 32. Typical Register Pointer Set
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Links: INA3221