Datasheet

INA3221
www.ti.com SBOS576A –MAY 2012–REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS: V
S
= +3.3 V
At T
A
= +25°C, VIN+ = 12 V, V
SENSE
= (VIN+) – (VIN–) = 0 mV, and V
BUS
= 12 V, unless otherwise noted.
INA3221
PARAMETER CONDITIONS MIN TYP MAX UNIT
INPUT
Shunt –163.84 163.8 mV
Voltage input range
Bus 0 26 V
CMR Common-mode rejection VIN+ = 0 V to +26 V 110 120 dB
±40 ±80 μV
V
OS
Shunt T
A
= –40°C to +125°C 0.1 0.5 μV/°C
PSRR vs power supply, V
S
= +2.7 V to +5.5 V 15 μV/V
Offset voltage,
RTI
(1)
±8 ±16 mV
V
OS
Bus T
A
= –40°C to +125°C 80 μV/°C
PSRR vs power supply 0.5 mV/V
I
IN+
10 μA
Input bias current
I
IN–
10 || 670 μA || kΩ
Input leakage
(2)
(VIN+ pin) + (VIN– pin), power-down mode 0.1 0.5 μA
DC ACCURACY
ADC native resolution 13 Bits
Shunt voltage 40 μV
1-LSB step size
Bus voltage 8 mV
0.1 0.25 %
Shunt
T
A
= –40°C to +125°C 10 50 ppm/°C
Voltage gain error
0.1 0.25 %
Bus
T
A
= –40°C to +125°C 10 50 ppm/°C
DNL Differential nonlinearity ±0.1 LSB
CT bit = 000 140 154 µs
CT bit = 001 204 224 µs
CT bit = 010 332 365 µs
CT bit = 011 588 646 µs
t
CONVERT
ADC conversion time
CT bit = 100 1.1 1.21 ms
CT bit = 101 2.116 2.328 ms
CT bit = 110 4.156 4.572 ms
CT bit = 111 8.244 9.068 ms
SMBus
SMBus timeout
(3)
28 35 ms
DIGITAL INPUT/OUTPUT
C
I
Input capacitance 3 pF
Leakage input current 0 V ≤ V
IN
≤ V
S
0.1 1 μA
V
IH
0.7 (V
S
) 6 V
Input logic levels
V
IL
–0.5 0.3 (V
S
) V
SDA, critical, warning, PV V
S
> +2.7 V, I
OL
= 3 mA 0 0.4 V
V
OL
Output logic levels
TC V
S
> +2.7 V, I
OL
= 1.2 mA 0 0.4 V
V
hys
Hysteresis voltage 500 mV
(1) RTI = Referred-to-input.
(2) Input leakage is positive (current flows into the pin) for the conditions shown at the top of this table. Negative leakage currents can occur
under different input conditions.
(3) SMBus timeouts in the INA3221 reset the interface whenever SCL is low for more than 28 ms.
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