Datasheet

INA3221
www.ti.com SBOS576A –MAY 2012–REVISED JUNE 2013
Configuration Register (Address = 00h, Read/Write)
BIT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NAME RST CH1
en
CH2
en
CH3
en
AVG2 AVG1 AVG0 V
BUS
CT2 V
BUS
CT1 V
BUS
CT0 V
SH
CT2 V
SH
CT1 V
SH
CT0 MODE3 MODE2 MODE1
POR
0 1 1 1 0 0 0 1 0 0 1 0 0 1 1 1
VALUE
Bit 15 RST: Reset bit
Setting this bit to '1' generates a system reset that is the same as a power-on reset (POR). This bit resets all
registers to default values and self-clears.
Bits[14:12] CHEN: Channel enable mode
The channel enable mode bits allow each channel to be independently enabled or disabled.
0 = Channel disable
1 = Channel enable (default)
Bits[11:9] AVG: Averaging mode
Sets the number of samples that are collected and averaged together.
Table 3 summarizes the AVG bit settings and related number of averages for each bit.
Table 3. AVG Bit Settings, Bits[11:9]
AVG2 AVG1 AVG0 NUMBER OF
D11 D10 D9 AVERAGES
0 (default) 0 (default) 0 (default) 1 (default)
0 0 1 4
0 1 0 16
0 1 1 64
1 0 0 128
1 0 1 256
1 1 0 512
1 1 1 1024
Bits[8:6] V
BUS
CT: Bus voltage conversion time
Sets the conversion time for the bus voltage measurement.
Table 4 shows the V
BUS
CT bit options and related conversion times for each bit.
Table 4. V
BUS
CT Bit Settings, Bits[8:6]
V
BUS
CT2 V
BUS
CT1 V
BUS
CT0
CONVERSION TIME
D8 D7 D6
0 0 0 140 µs
0 0 1 204 µs
0 1 0 332 µs
0 1 1 588 µs
1 (default) 0 (default) 0 (default) 1.1 ms (default)
1 0 1 2.116 ms
1 1 0 4.156 ms
1 1 1 8.244 ms
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