Datasheet

INA220
www.ti.com SBOS459D –JUNE 2009–REVISED SEPTEMBER 2010
APPLICATION INFORMATION
The INA220 is a digital current-shunt monitor with an
Data transfer is then initiated and eight bits of data
Two-Wire and SMBus-compatible interface. It
are sent, followed by an Acknowledge bit. During
provides digital current, voltage, and power readings
data transfer, SDA must remain stable while SCL is
necessary for accurate decision-making in
HIGH. Any change in SDA while SCL is HIGH is
precisely-controlled systems. Programmable registers
interpreted as a START or STOP condition.
allow flexible configuration for measurement
resolution, and continuous-versus-
Once all data have been transferred, the master
triggered operation. Detailed register information
generates a STOP condition, indicated by pulling
appears at the end of this data sheet, beginning with
SDA from LOW to HIGH while SCL is HIGH. The
Table 3. See the Register Block Diagram for a block
INA220 includes a 28ms timeout on its interface to
diagram of the INA220.
prevent locking up an SMBus.
INA220 TYPICAL APPLICATION Serial Bus Address
The figure on the front page shows a typical To communicate with the INA220, the master must
application circuit for the INA220. Use a 0.1mF first address slave devices via a slave address byte.
ceramic capacitor for power-supply bypassing, placed The slave address byte consists of seven address
as closely as possible to the supply and ground pins. bits, and a direction bit indicating the intent of
executing a read or write operation.
The input filter circuit consisting of R
F1
, R
F2
, and C
F
is
not necessary in most applications. If the need for The INA220 has two address pins, A0 and A1.
filtering is unknown, reserve board space for the Table 1 describes the pin logic levels for each of the
components and install 0Ω resistors unless a filter is 16 possible addresses. The state of pins A0 and A1
needed. See the Filtering and Input Considerations is sampled on every bus communication and should
section. be set before any activity on the interface occurs. The
address pins are read at the start of each
communication event.
BUS OVERVIEW
The INA220 offers compatibility with both Two-Wire
Table 1. INA220 Address Pins and
and SMBus interfaces. The Two-Wire and SMBus
Slave Addresses
protocols are essentially compatible with one another.
A1 A0 SLAVE ADDRESS
The Two-Wire interface is used throughout this data
GND GND 1000000
sheet as the primary example, with SMBus protocol
GND V
S+
1000001
specified only when a difference between the two
GND SDA 1000010
systems is being addressed. Two bidirectional lines,
GND SCL 1000011
SCL and SDA, connect the INA220 to the bus. Both
SCL and SDA are open-drain connections.
V
S+
GND 1000100
V
S+
V
S+
1000101
The device that initiates the transfer is called a
master, and the devices controlled by the master are V
S+
SDA 1000110
slaves. The bus must be controlled by a master
V
S+
SCL 1000111
device that generates the serial clock (SCL), controls
SDA GND 1001000
the bus access, and generates START and STOP
SDA V
S+
1001001
conditions.
SDA SDA 1001010
To address a specific device, the master initiates a
SDA SCL 1001011
START condition by pulling the data signal line (SDA)
SCL GND 1001100
from a HIGH to a LOW logic level while SCL is HIGH.
SCL V
S+
1001101
All slaves on the bus shift in the slave address byte
on the rising edge of SCL, with the last bit indicating
SCL SDA 1001110
whether a read or write operation is intended. During
SCL SCL 1001111
the ninth clock pulse, the slave being addressed
responds to the master by generating an
Acknowledge and pulling SDA LOW.
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