Datasheet

C
BYPASS
0.1 F
(typical)
m
Supply Voltage
(INA219PowerSupplyRangeis
3Vto5.5V)
Data(SDA)
Clock(SCL)
´
PowerRegister
CurrentRegister
I C
Interface
2
VoltageRegister
V
IN+
R
F1
R
F2
R
PULLUP
3.3k
(typical)
W
R
PULLUP
3.3k
(typical)
W
V
IN-
ADC
PGA
INA219
GND
PowerBus
(0Vto26V)
Load
Current
Shunt
C
F
A0
A1
SDA
SCL
INA219
www.ti.com SBOS448F –AUGUST 2008– REVISED SEPTEMBER 2011
APPLICATION INFORMATION
The INA219 is a digital current-shunt monitor with an The I
2
C interface is used throughout this data sheet
I
2
C and SMBus-compatible interface. It provides as the primary example, with SMBus protocol
digital current, voltage, and power readings specified only when a difference between the two
necessary for accurate decision-making in systems is being addressed. Two bidirectional lines,
precisely-controlled systems. Programmable registers SCL and SDA, connect the INA219 to the bus. Both
allow flexible configuration for measurement SCL and SDA are open-drain connections.
resolution, and continuous-
The device that initiates the transfer is called a
versus-triggered operation. Detailed register
master, and the devices controlled by the master are
information appears at the end of this data sheet,
slaves. The bus must be controlled by a master
beginning with Table 4. See the Register Block
device that generates the serial clock (SCL), controls
Diagram for a block diagram of the INA219.
the bus access, and generates START and STOP
conditions.
INA219 TYPICAL APPLICATION
To address a specific device, the master initiates a
Figure 13 shows a typical application circuit for the
START condition by pulling the data signal line (SDA)
INA219. Use a 0.1μF ceramic capacitor for
from a HIGH to a LOW logic level while SCL is HIGH.
power-supply bypassing, placed as closely as
All slaves on the bus shift in the slave address byte
possible to the supply and ground pins.
on the rising edge of SCL, with the last bit indicating
whether a read or write operation is intended. During
The input filter circuit consisting of R
F1
, R
F2
, and C
F
is
the ninth clock pulse, the slave being addressed
not necessary in most applications. If the need for
responds to the master by generating an
filtering is unknown, reserve board space for the
Acknowledge and pulling SDA LOW.
components and install 0Ω resistors unless a filter is
needed. See the Filtering and Input Considerations
Data transfer is then initiated and eight bits of data
section.
are sent, followed by an Acknowledge bit. During
data transfer, SDA must remain stable while SCL is
The pull-up resistors shown on the SDA and SCL
HIGH. Any change in SDA while SCL is HIGH is
lines are not needed if there are pull-up resistors on
interpreted as a START or STOP condition.
these same lines elsewhere in the system. Resistor
values shown are typical: consult either the I
2
C or
Once all data have been transferred, the master
SMBus specification to determine the acceptable
generates a STOP condition, indicated by pulling
minimum or maximum values.
SDA from LOW to HIGH while SCL is HIGH. The
INA219 includes a 28ms timeout on its interface to
BUS OVERVIEW
prevent locking up an SMBus.
The INA219 offers compatibility with both I
2
C and
SMBus interfaces. The I
2
C and SMBus protocols are
essentially compatible with one another.
Figure 13. Typical Application Circuit
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