Datasheet

SCL
SDA
t
(LOW)
t
R
t
F
t
(HDSTA)
t
(HDSTA)
t
(HDDAT)
t
(BUF)
t
(SUDAT)
t
(HIGH)
t
(SUSTA)
t
(SUSTO)
P S S P
INA219
www.ti.com SBOS448F –AUGUST 2008– REVISED SEPTEMBER 2011
High-Speed I
2
C Mode
The master then generates a repeated start condition
When the bus is idle, both the SDA and SCL lines are
(a repeated start condition has the same timing as
pulled high by the pull-up devices. The master
the start condition). After this repeated start condition,
generates a start condition followed by a valid serial
the protocol is the same as F/S mode, except that
byte containing High-Speed (HS) master code
transmission speeds up to 3.4Mbps are allowed.
00001XXX. This transmission is made in fast
Instead of using a stop condition, repeated start
(400kbps) or standard (100kbps) (F/S) mode at no
conditions should be used to secure the bus in
more than 400kbps. The INA219 does not
HS-mode. A stop condition ends the HS-mode and
acknowledge the HS master code, but does
switches all the internal filters of the INA219 to
recognize it and switches its internal filters to support
support the F/S mode.
3.4Mbps operation.
Figure 18. Bus Timing Diagram
Bus Timing Diagram Definitions
FAST MODE HIGH-SPEED MODE
PARAMETER MIN MAX MIN MAX UNITS
SCL Operating Frequency f
(SCL)
0.001 0.4 0.001 3.4 MHz
Bus Free Time Between STOP and START
t
(BUF)
600 160 ns
Condition
Hold time after repeated START condition.
t
(HDSTA)
100 100 ns
After this period, the first clock is generated.
Repeated START Condition Setup Time t
(SUSTA)
100 100 ns
STOP Condition Setup Time t
(SUSTO)
100 100 ns
Data Hold Time t
(HDDAT)
0 0 ns
Data Setup Time t
(SUDAT)
100 10 ns
SCL Clock LOW Period t
(LOW)
1300 160 ns
SCL Clock HIGH Period t
(HIGH)
600 60 ns
Clock/Data Fall Time t
F
300 160 ns
Clock/Data Rise Time t
R
300 160 ns
Clock/Data Rise Time for SCLK ≤ 100kHz t
R
1000 ns
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