Datasheet

Gain Error Factor =
(1250 ´
INT
R )
(1250
S
´ ´ ´R ) + (1250 R ) + (R R )
INT S INT
R
SHUNT
V
REF
V
OUT
V+
V
CM
R < 10W
S
R
INT
R < 10
S
W
R
INT
Load
C
F
Bias
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SBOS437F –MAY 2008–REVISED JUNE 2014 www.ti.com
8.4 Device Functional Modes
8.4.1 Input Filtering
An obvious and straightforward filtering location is at the device output. However, this location negates the
advantage of the low output impedance of the internal buffer. The only other filtering option is at the device input
pins. This location, though, does require consideration of the ±30% tolerance of the internal resistances.
Figure 24 shows a filter placed at the inputs pins.
Figure 24. Filter at Input Pins
The addition of external series resistance, however, creates an additional error in the measurement so the value
of these series resistors should be kept to 10Ω or less if possible to reduce impact to accuracy. The internal bias
network shown in Figure 24 present at the input pins creates a mismatch in input bias currents when a
differential voltage is applied between the input pins. If additional external series filter resistors are added to the
circuit, the mismatch in bias currents results in a mismatch of voltage drops across the filter resistors. This
mismatch creates a differential error voltage that subtracts from the voltage developed at the shunt resistor. This
error results in a voltage at the device input pins that is different than the voltage developed across the shunt
resistor. Without the additional series resistance, the mismatch in input bias currents has little effect on device
operation. The amount of error these external filter resistor add to the measurement can be calculated using
Equation 2 where the gain error factor is calculated using Equation 1.
The amount of variance in the differential voltage present at the device input relative to the voltage developed at
the shunt resistor is based both on the external series resistance value as well as the internal input resistors, R3
and R4 (or R
INT
as shown in Figure 24). The reduction of the shunt voltage reaching the device input pins
appears as a gain error when comparing the output voltage relative to the voltage across the shunt resistor. A
factor can be calculated to determine the amount of gain error that is introduced by the addition of external series
resistance. The equation used to calculate the expected deviation from the shunt voltage to what is seen at the
device input pins is given in Equation 1:
where:
• R
INT
is the internal input resistor (R3 and R4), and
• R
S
is the external series resistance. (1)
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