Datasheet

FUNCTIONAL BLOCK DIAGRAM
ADC
DAC
´ ´
ShuntVoltage
Channel
BusV
oltage
Channel
PGA
(InConfigurationRegister)
ShuntVoltage
(1)
DataRegisters
Full-ScaleCalibration
(2)
Current
(1)
BusVoltage
(1)
Power
(1)
ShuntV
oltage Peak-
(2)
ShuntV
oltage+Peak
(2)
Peak-HoldRegisters
BusV
oltage
MinimumPeak
(2)
BusVoltage
MaximumPeak
(2)
PowerPeak
(2)
CMP CMP
CMP CMP CMP CMP CMP CMP CMP CMP
ShuntV
oltage Warning-
(2)
ShuntV
oltage+Warning
(2)
BusVoltageUnder-
VoltageWarning
(2)
ProgrammableDelay
(setin
CriticalDAC Register)-
Latchand
Polarity
BusV
oltageOver
-
VoltageWarning
(2)
PowerW
arning
(2)
BusUnder-Voltage Over-limit
(2)
BusOver-Voltage Over-limit
(2)
Power Over-limit
(2)
Enable/Disable
inSMBus/Enable
Register
W
arning
(Open-Drain)
Latchand
Polarity
Enable/Disable
inSMBus/Enable
Register
Over-limit
(Open-Drain)
WarningOutputDefault:
· Disabled
· ActiveLow
· Transparent(notlatched)
ProgrammableDelay
(setin
CriticalDAC Register)-
Latchand
Polarity
Enable/Disable
inSMBus/Enable
Register
Critical
(Open-Drain)
CriticalOutputDefault:
· Disabled
· ActiveLow
· Transparent(notlatched)
WarningRegistersandOutput
OverlimitOutputDefault:
·
Disabled
· ActiveLow
· Transparent(notlatched)
OverlimitRegistersandOutput
CriticalDAC+
(2)
DAC
CriticalDAC-
(2)
CriticalDACHysteresis
NOTES:DashedlineindicatestheflagisintheStatusRegister.
(1)Read-only.
(2)Read/Write.
INA209
www.ti.com ......................................................................................................................................................... SBOS403B – JUNE 2007 – REVISED MARCH 2009
Figure 14.
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