Datasheet

Critical DAC – Register (Critical Shunt Negative Voltage) 15h (Read/Write)
INA209
SBOS403B – JUNE 2007 – REVISED MARCH 2009 ......................................................................................................................................................... www.ti.com
No sign bit (sets negative limit only). At full-scale range = – 255mV; LSB = 1mV; 8-bit.
BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
BIT
CDP7 CDP6 CDP5 CDP4 CDP3 CDP2 CDP1 CDP0 CF3 CF2 CF1 CF0 WD3 WD2 WD1 WD0
NAME
POR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VALUE
Bit Descriptions
CDP: Critical DAC- limit setting.
Bits 15 – 8
CF: Configures DAC Comparator output filter.
Bits 7 – 4 Ranges from 0 to 0.96ms; 64s/LSB. CF settings are listed in Table 9 .
WD: Configures Warning pin Output Delay from 0 to 1.5s; 0.1 second/LSB.
Bits 3 – 0 Default = 0. WD settings are listed in Table 10 .
Table 9. CF Settings
FILTER SETTING
CF3 CF2 CF1 CF0 (ms)
0 0 0 0 0
0 0 0 1 0.064
0 0 1 0 0.128
0 0 1 1 0.192
0 1 0 0 0.256
0 1 0 1 0.320
0 1 1 0 0.384
0 1 1 1 0.448
1 0 0 0 0.512
1 0 0 1 0.576
1 0 1 0 0.640
1 0 1 1 0.704
1 1 0 0 0.768
1 1 0 1 0.832
1 1 1 0 0.896
1 1 1 1 0.960
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