Datasheet
Critical DAC+ Register (Critical Shunt Positive Voltage) 14h (Read/Write)
INA209
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......................................................................................................................................................... SBOS403B – JUNE 2007 – REVISED MARCH 2009
No sign bit (sets a positive limit only). At full-scale range = 255mV; LSB = 1mV; 8-bit.
BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
BIT CHYST CHYST CHYST
CDP7 CDP6 CDP5 CDP4 CDP3 CDP2 CDP1 CDP0 GP GMP1 GPM0 CP CRL
NAME 2 1 0
POR
0 0 0 0 0 0 0 0 x
(1)
0 0 0 0 0 0 0
VALUE
(1) POR value reflects the state of the GPIO pin.
Bit Descriptions
CDP: Critical DAC+ limit setting.
Bits 15 – 8
GP: GPIO read back.
Bit 7 Shows state of the GPIO pin.
GPM: GPIO mode bit.
Bits 6, 5 The GPIO mode settings are shown in Table 7 .
Table 7. GPIO Mode Settings
(1)
GPM1 GPM0 STATE NOTES
0 0 Hi-Z
Use as an input in either of these
modes.
0 1 Hi-Z
1 0 0
1 1 1
(1) Shaded values are default.
CP: Configures the Critical output pin polarity (open-drain output).
Bit 4 1 = Active high
0 = Active low (default)
CHYST: Configures Critical comparator hysteresis.
Bits 3 – 1 The CHYST settings are shown in Table 8 .
Table 8. CHYST Settings
(1)
CHYST2 CHYST1 CHYST0 HYSTERESIS
0 0 0 0mV
0 0 1 2mV
0 1 0 4mV
0 1 1 6mV
1 0 0 8mV
1 0 1 10mV
1 1 0 12mV
1 1 1 14mV
(1) Shaded values are default.
CRL: Configures Critical pin latch feature.
Bit 0 1 = Latch enabled
0 = Transparent (default)
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