Datasheet

INA209
www.ti.com ......................................................................................................................................................... SBOS403B – JUNE 2007 – REVISED MARCH 2009
SMBus Alert Mask/Enable Control Register 02h (Read/Write)
BIT # D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
BIT
MWOV MWUV MWP MWS+ MWS – MOLOV MOLUV MOLP MCRIT+ MCRIT – MCNVR — SMAEN CREN OLEN WRNEN
NAME
POR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VALUE
Bits D5 – D15 of the SMBus Alert Mask Register mask correspond to bits D5 to D15 of the Status Register to
prevent them from initiating an SMBus Alert. It does not prevent the Status Register bit from setting. Writing a '0'
to an SMBus Alert Mask bit masks it from activating the SMBus Alert. All default values are '0'.
Bit Descriptions
MWOV: Warning Bus Over-Voltage Mask
Bit 15 When set to '0', this bit masks the WOV bit of the Status Register.
MWUV: Warning Bus Under-Voltage Mask
Bit 14 When set to '0', this bit masks the WUV bit of the Status Register.
MWP: Warning Power Mask
Bit 13 When set to '0', this bit masks the WP bit of the Status Register.
MWS+: Warning Shunt Positive Voltage Mask
Bit 12 When set to '0', this bit masks the WS+ bit of the Status Register.
MWS – : Warning Shunt Negative Voltage Mask
Bit 11 When set to '0', this bit masks the WS – bit of the Status Register.
MOLOV: Over-Limit Bus Over-Voltage Mask
Bit 10 When set to '0', this bit masks the OLOV bit of the Status Register.
MOLUV: Over-Limit Bus Under-Voltage Mask
Bit 9 When set to '0', this bit masks the OLUV bit of the Status Register.
MOLP: Over-Limit Power Mask
Bit 8 When set to '0', this bit masks the OLP bit of the Status Register.
MCRIT+: Critical Shunt Positive Voltage Mask
Bit 7 When set to '0', this bit masks the CRIT+ bit of the Status Register.
MCRIT – : Critical Shunt Negative Voltage Mask
Bit 6 When set to '0', this bit masks the CRIT – bit of the Status Register.
MCNVR: Conversion Ready Mask
Bit 5 When set to '0', this bit masks the CNVR bit of the Status Register.
SMAEN: SMBus Alert Enable
Bit 3 1 = Enable SMBus Alert
0 = Disable SMBus Alert (default)
CREN: Critical DAC Enable
Bit 2 Enables/disables operation of the Critical pin output.
1 = Enabled
0 = Disabled (default)
OLEN: Over-Limit Enable
Bit 1 Enables/disables operation of the Overlimit pin output.
1 = Enabled
0 = Disabled (default)
WRNEN: Warning Enable
Bit 0 Enables/disables operation of the Warning pin output.
1 = Enabled
0 = Disabled (default)
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