Datasheet

All Other Latches
Multichannel Data Acquisition
Gnd
V
S
V
IN-
V
IN+
Warning
Overlimit
Critical
Convert
Data
Clk
Alert
GPIO
I C
2
Bus
INA209
Gnd
V
S
V
IN-
V
IN+
Warning
Overlimit
Critical
Convert
Data
Clk
Alert
INA209
Gnd
V
S
V
IN-
V
IN+
Warning
Overlimit
Critical
Convert
Data
Clk
Alert
INA209
Gnd
V
S
V
IN-
V
IN+
Warning
Overlimit
Critical
Convert
Data
Clk
Alert
INA209
INA209
www.ti.com ......................................................................................................................................................... SBOS403B – JUNE 2007 – REVISED MARCH 2009
quick fault identification for simple slave devices.
When an ALERT occurs, the master can broadcast
the alert response slave address (0001 100).
Following this alert response, any slave devices that
generated interrupts identify themselves by putting
the respective addresses on the bus.
The alert response can activate several different
slave devices simultaneously, similar to the I
2
C
General Call. If more than one slave attempts to
respond, bus arbitration rules apply; the device with
the lower address code wins. The losing device does
not generate an Acknowledge and continues to hold
the ALERT line low until the interrupt is cleared.
Successful completion of the read alert response
protocol clears the SMBus ALERT pin, provided that
the condition causing the alert no longer exists. The
SMBus Alert flag is cleared separately by either
reading the Status Register or by disabling the
SMBus Alert function.
The Status Register flags indicate which (if any) of
the watchdogs have been activated. After power-on
reset (POR), the normal state of all flag bits is '0',
assuming that no alarm conditions exist. The flags
are cleared by any successful read of the Status
Register, after a conversion is complete and the fault
no longer exists.
The latches in the Configuration Register for the
Warning, Over-Limit, and Critical outputs are not
associated with the SMBus alert response, and are
cleared whenever the Status Register is read. If the
fault remains, they continue to set (they may also be
cleared by setting the latch enable to transparent,
and then returning it to latch mode).
The values in the Peak-Hold Registers must be
cleared by writing a '1' to the respective LSBs.
The INA209 can be used in multiple current
measurement channels where the controlling
processor sums the currents of all the channels for a
total current. Often these current measurements must
occur simultaneously. Use the GPIO output from one
of the INA209s and connect it to the Convert pin of
Figure 23. Multichannel Data Acquisition with
the other INA209s. This architecture allows for
Simultaneous Sampling
sending conversion commands via the I
2
C bus to the
master device, and all devices will convert
simultaneously. Figure 23 illustrates this architecture
using four INA209s.
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Product Folder Link(s): INA209