Datasheet
High-Speed I
2
C Mode
SCL
SDA
t
(LOW)
t
R
t
F
t
(HDSTA)
t
(HDSTA)
t
(HDDAT)
t
(BUF)
t
(SUDAT)
t
(HIGH)
t
(SUSTA)
t
(SUSTO)
P S S P
INA209
SBOS403B – JUNE 2007 – REVISED MARCH 2009 .........................................................................................................................................................
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The master then generates a repeated start condition
(a repeated start condition has the same timing as
When the bus is idle, both the SDA and SCL lines are
the start condition). After this repeated start condition,
pulled high by the pull-up devices. The master
the protocol is the same as F/S mode, except that
generates a start condition followed by a valid serial
transmission speeds up to 3.4Mbps are allowed.
byte containing High-Speed (HS) master code
Instead of using a stop condition, repeated start
00001XXX. This transmission is made in fast
conditions should be used to secure the bus in
(400kbps) or standard (100kbps) (F/S) mode at no
HS-mode. A stop condition ends the HS-mode and
more than 400kbps. The INA209 does not
switches all the internal filters of the INA209 to
acknowledge the HS master code, but does
support the F/S mode.
recognize it and switches its internal filters to support
3.4Mbps operation.
Figure 20. Bus Timing Diagram
Bus Timing Diagram Definitions
FAST MODE HIGH-SPEED MODE
PARAMETER MIN MAX MIN MAX UNITS
SCL Operating Frequency f
(SCL)
0.001 0.4 0.001 3.4 MHz
Bus Free Time Between STOP and START
t
(BUF)
600 160 ns
Condition
Hold time after repeated START condition.
t
(HDSTA)
100 100 ns
After this period, the first clock is generated.
Repeated START Condition Setup Time t
(SUSTA)
100 100 ns
STOP Condition Setup Time t
(SUSTO)
100 100 ns
Data Hold Time t
(HDDAT)
0 0 ns
Data Setup Time t
(SUDAT)
100 10 ns
SCL Clock LOW Period t
(LOW)
1300 160 ns
SCL Clock HIGH Period t
(HIGH)
600 60 ns
Clock/Data Fall Time t
F
300 160 ns
Clock/Data Rise Time t
R
300 160 ns
Clock/Data Rise Time for SCLK ≤ 100kHz t
R
1000 ns
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