Datasheet

APPLICATION INFORMATION
BUS OVERVIEW
C
BYPASS
0.1 Fm
Supply
Load
Current
Shunt
Supply Voltage
(INA209PowerSupplyRangeis
3Vto5.5V)
3.3VSupply
CriticalOutput
OverlimitOutput
WarningOutput
Data(SDA)
Alert
Clock(SCL)
Critical
DAC+
Critical
DAC -
´
CMP
CMP
Filter
Watchdog
PowerRegister
CurrentRegister
I C
2
Interface
VoltageRegister
Convert
ADC
GND GPIO
INA209
V
IN+
V
IN-
V
S
INA209
SBOS403B – JUNE 2007 – REVISED MARCH 2009 ......................................................................................................................................................... www.ti.com
The INA209 is a digital current-shunt monitor with an To address a specific device, the master initiates a
I
2
C and SMBus-compatible interface. It provides START condition by pulling the data signal line (SDA)
digital current, voltage, and power readings from a HIGH to a LOW logic level while SCL is HIGH.
necessary for accurate decision-making in All slaves on the bus shift in the slave address byte
precisely-controlled systems. Programmable registers on the rising edge of SCL, with the last bit indicating
allow flexible configuration for setting warning limits, whether a read or write operation is intended. During
measurement resolution, and continuous- the ninth clock pulse, the slave being addressed
versus-triggered operation. Detailed register responds to the master by generating an
information appears at the end of this data sheet, Acknowledge and pulling SDA LOW.
beginning with Table 2 . See the Functional Block
Data transfer is then initiated and eight bits of data
Diagram for a block diagram of the INA209.
are sent, followed by an Acknowledge bit. During
The INA209 offers compatability with I
2
C and SMBus data transfer, SDA must remain stable while SCL is
interfaces. The I
2
C and SMBus protocols are HIGH. Any change in SDA while SCL is HIGH is
essentially compatible with each other. I
2
C will be interpreted as a START or STOP condition.
used throughout this document, with SMBus being
Once all data have been transferred, the master
specified only when a difference between the two
generates a STOP condition, indicated by pulling
systems is being addressed. Two bi-directional lines,
SDA from LOW to HIGH while SCL is HIGH. The
SCL and SDA, connect the INA209 to the bus. Both
INA209 includes a 28ms timeout on its interface to
SCL and SDA are open-drain connections. Figure 15
prevent locking up an SMBus.
shows a typical application circuit.
The device that initiates the transfer is called a
master, and the devices controlled by the master are
slaves. The bus must be controlled by a master
device that generates the serial clock (SCL), controls
the bus access, and generates START and STOP
conditions.
Figure 15. Typical Application Circuit
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