Datasheet
INA159
SBOS333B − JULY 2005 − REVISED OCTOBER 2005
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3
ELECTRICAL CHARACTERISTICS: V
S
= +5V
Boldface limits apply over the specified temperature range, T
A
= −40°C to +125°C.
At T
A
= +25°C, R
L
= 10kΩ connected to V
S
/2, REF pin 1 connected to ground, and REF pin 2 connected to V
REF
= 5V, unless otherwise noted.
INA159
PARAMETER CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
(1)
RTO
Initial
(1)
V
OS
V
S
= ±2.5V, Reference and Input Pins Grounded ±100 ±500 µV
vs Temperature ±1.5 µV/°C
vs Power Supply PSRR V
S
= ±0.9V to ±2.75V ±20 ±100 µV/V
Reference Divider Accuracy
(2)
±0.002 ±0.024 %
over Temperature ±0.002 %
INPUT IMPEDANCE
(3)
Differential 240 kΩ
Common-Mode 60 kΩ
INPUT VOLTAGE RANGE RTI
Common-Mode Voltage
Range
V
CM
Positive 17.5 V
Negative −12.5 V
Common-Mode Rejection
Ratio
CMRR V
CM
= −10V to +10V, R
S
= 0Ω 80 96 dB
over Temperature 94 dB
OUTPUT VOLTAGE NOISE
(4)
RTO
f = 0.1Hz to 10Hz 10 µV
PP
f = 10kHz 30 nV/√Hz
GAIN V
REF2
= 4.096V, R
L
Connected to GND,
(V
IN+
) − (V
IN−
) = −10V to +10V, V
CM
= 0V
Initial G 0.2 V/V
Error ±0.005 ±0.024 %
vs Temperature ±1 ppm/°C
Nonlinearity ±0.0002 % of FS
OUTPUT
Voltage, Positive V
REF2
= 4.096V, R
L
Connected to GND (V+) − 0.1 (V+) − 0.02 V
Voltage, Negative V
REF2
= 4.096V, R
L
Connected to GND (V−) + 0.048 (V−) + 0.01 V
Current Limit, Continuous to Common ±60 mA
Capacitive Load See Typical Characteristic pF
Open-Loop Output Impedance R
O
f = 1MHz, I
O
= 0 110 Ω
FREQUENCY RESPONSE
Small-Signal Bandwidth −3dB 1.5 MHz
Slew Rate SR 15 V/µs
Settling Time, 0.01% t
S
4V Output Step, C
L
= 100pF 1 µs
Overload Recovery Time 50% Overdrive 250 ns
POWER SUPPLY
Specified Voltage Range V
S
+5 V
Operating Voltage Range +1.8 +5.5 V
Quiescent Current I
Q
I
O
= 0mA, V
S
= ±2.5V,
Reference and Input Pins Grounded
1.1 1.5 mA
TEMPERATURE RANGE
Specified Range −40 +125 °C
Operating Range −40 +150 °C
Storage Range −65 +150 °C
Thermal Resistance q
JA
MSOP-8 Surface-Mount 150 °C/W
(1)
Includes effects of amplifier input bias and offset currents.
(2)
Reference divider accuracy specifies the match between the reference divider resistors using the configuration in Figure 2.
(3)
Internal resistors are ratio matched but have ±20% absolute value.
(4)
Includes effects of amplifier input current noise and thermal noise contribution of resistor network.