Datasheet
INA110
9
SBOS147A
www.ti.com
GAIN SELECTION
Gain selection is accomplished by connecting the appropri-
ate pins together on the INA110. Table I shows possible
gains from the internal resistors. Keep the connections as
short as possible to maintain accuracy.
Gains other than 1, 10, 100, 200, and 500 can be set by
adding an external resistor, R
G
, between pin 3 and pins 12,
16, and 11. Gain accuracy is a function of R
G
and the
internal resistors which have a ±20% tolerance with
20ppm/°C drift. The equation for choosing R
G
is shown
below.
Gain can also be changed in the output stage by adding
resistance to the feedback loop shown in Figure 4. This is
useful for increasing the total gain or reducing the input
stage gain to prevent saturation of input amplifiers.
The output gain can be changed as shown in Table II.
Matching of R
1
and R
3
is required to maintain high CMR. R
2
sets the gain with no effect on CMR.
CONNECT PIN 3 GAIN GAIN
GAIN TO PIN ACCURACY (%) DRIFT (ppm/
°C)
The following gains have assured accuracy:
1 none 0.02 10
10 13 0.05 10
100 12 0.1 20
200 16 0.2 30
500 11 0.5 50
The following gains have typical accuracy as shown:
300 12, 16 0.25 10
600 11, 12 0.25 40
700 11, 16 2 40
800 11, 12, 16 2 80
TABLE I. Internal Gain Connections.
are eliminated since they are inside the feedback loop.
Proper connection is shown in Figure 1. When more current
is to be supplied, a power booster can be placed within the
feedback loop as shown in Figure 5. Buffer errors are
minimized by the loop gain of the output amplifier.
FIGURE 4. Gain Adjustment of Output Stage Using H Pad
Attenuator.
FIGURE 5. Current Boosting the Output.
3553
1
6
10
INA110
9
V
OUT
R
L
∆V
IN
2
I
L
= 100mA
Sense
G –1
40kΩ
R
G
= – 50Ω
OUTPUT STAGE GAIN R
1
AND R
3
R
2
21.2kΩ 2.74kΩ
51kΩ 511Ω
10 1.5kΩ 340Ω
TABLE II. Output Stage Gain Control.
COMMON-MODE INPUT RANGE
It is important not to exceed the input amplifiers’ dynamic
range (see Typical Characteristics). The differential input
signal and its associated common-mode voltage should not
cause the output of A
1
and A
2
(input amplifiers) to exceed
approximately ±10V with ±15V supplies or nonlinear opera-
tion will result. Such large common-mode voltages, when
the INA110 is in high gain, can cause saturation of the input
stage even though the differential input is very small. This
can be avoided by reducing the input stage gain and increas-
ing the output stage gain with an H pad attenuator (see
Figure 4).
OUTPUT SENSE
An output sense has been provided to allow greater accuracy
in connecting the load. By attaching this feedback point to
the load at the load site, IR drops due to load currents that
LOW BIAS CURRENT
OF FET INPUT ELIMINATES DC ERRORS
Because the INA110 has FET inputs, bias currents drawn
through input source resistors have a negligible effect on DC
accuracy. The picoamp levels produce no more than micro-
volts through megohm sources. Thus, input filtering and
input series protection are readily achievable.
A return path for the input bias currents must always be
provided to prevent charging of stray capacitance. Other-
wise, the output can wander and saturate. A 1MΩ to 10MΩ
resistor from the input to common will return floating
sources such as transformers, thermocouples, and
AC-coupled inputs (see Applications section).
DYNAMIC PERFORMANCE
The INA110 is a fast-settling FET input instrumentation
amplifier. Therefore, careful attention to minimize stray
capacitance is necessary to achieve specified performance.
High source resistance will interact with input capacitance to
reduce the overall bandwidth. Also, to maintain stability,
avoid capacitance from the output to the gain set, offset
adjust, and input pins.
Applications with balanced-source impedance will provide
the best performance. In some applications, mismatched
source impedances may be required. If the impedance in the
1
6
10
INA110
9
V
OUT
R
3
∆V
IN
R
2
2
R
1
Output Stage Gain
=
(R
2
|| 20kΩ) + R
1
+ R
3
R
2
|| 20kΩ