Datasheet

start msb Chip Address lsb w ack msb Register Add lsb ack msb DATA lsb ack stop
ack from slave
ack from slave
SCL
SDA
start Id = TBDh w ack addr = 02h ack ack DGGUHVVK¶02 data stop
ack from slave
reg
addr_7
bit_7
MSB
bit_6 bit_5
AI
I
2
C SLAVE register address
bit_3 bit_2 bit_1 bit_0
LSB
1 2 3 4 5 6 7
bit_4
8
reg
addr_6
reg
addr_5
reg
addr_3
reg
addr_2
reg
addr_1
reg
addr_0
SDA
SCL
S P
S
TART condition STO
P
condition
www.ti.com I
2
C Compatible Interface
Figure 4. START and STOP Conditions
6.4 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being
transferred first. Each byte of data has to be followed by an acknowledge bit. All clock pulses are
generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock
pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A
receiver which has been addressed must generate an acknowledge after each byte has been received.
After the START condition, the I
2
C master sends a chip address. This address is seven bits long followed
by an eighth bit which is a data direction bit (R/W). The second byte selects the register to which the data
will be written. The third byte contains data to write to the selected register.
Figure 5. I
2
C Chip Address
Figure 6. I
2
C Write Cycle
w = write (SDA = '0')
r = read (SDA = '1')
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = chip address
5
SNVA343A–April 2008–Revised April 2013
AN-1840 USB I
2
C Interface Board Reference Manual
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated