Datasheet

FPD-Link Evaluation Kit User’s Manual
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 7 of 25
FPD-Link Transmitter Board Description:
J1 (60 position) accepts 28 bit LVTTL/LVCMOS data along with the clock.
The FPD-Link Transmitter board is powered externally. For the transmitter to be
operational, the Power Down pin must be set HIGH with a jumper. Rising or falling
edge reference clock is selected by JP1 tied to Vcc (rising) or GND (falling).
The 20-pin IDC connector (J2) provides the interface for LVDS signals for the
Receiver board.
Note: Previous HSL Tx/Rx 8 Bit boards have different IDC pinouts and must be
scrambled in the IDC cable in order to be compatible with this demo kit.
Vcc and Gnd MUST be
applied externally here
1 2
GND
TXIN0
GND
TXIN1
GND
TXIN2
GND
TXIN3
GND
TXIN4
GND
TXIN5
GND
TXIN6
GND
TXIN7
GND
TXIN8
GND
TXIN9
GND
TXIN10
GND
TXIN11
GND
TXIN12
GND
TXIN13
GND
TXIN14
GND
TXIN15
GND
TXIN16
GND
TXIN17
GND
TXIN18
GND
TXIN19
GND
TXIN20
GND
TXIN21
GND
TXIN22
GND
TXIN23
GND
TXIN24
GND
TXIN25
GND
TXIN26
GND
TXIN27
GND
TXCLKIN
GND GND
59 60
J1
/PD
TxOUT LVDS signals
20-pin IDC connector
60-pin IDC Connector
R_FB
1 2
GND
OUT0-
OUT0+
GND
GND
OUT1-
OUT1+
GND
GND
OUT2-
OUT2+
GND
GND
CLK-
CLK+
GND
GND
OUT3-
OUT3+
GND
19 20
J2
Note: Previous HSL Tx/Rx 8 Bit boards
have different IDC pinouts and must be
scrambled in the IDC cable in order to
be com
p
atible with this demo kit.