Datasheet

FPD-Link Evaluation Kit User’s Manual
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 20 of 25
RxOUT
The plot above shows both the recovered PRBS data and also the regenerated
Clock overlaid. Note that the clock transitions slightly before the data transition and
strobes the data on the falling edge of the clock. The data and clock signals are low
drive 3V CMOS outputs. The plot above is at 85MHz.