Datasheet

FPD-Link Evaluation Kit User’s Manual
National Semiconductor Corporation
Rev 3.0
Date: 9/25/2007
Page 12 of 25
Rx FPD-Link Receiver Board:
J1 (60 position) provides access to the 28 bit LVTTL/LVCMOS and clock outputs.
The FPD-Link Receiver board is powered from the pads show below. For the
receiver to be operational, the Power Down pin must be set HIGH with the jumper.
The 20-pin IDC connector (J2) provides the interface for LVDS signals for the
Receiver board.
Note: Previous HSL Tx/Rx 8 Bit boards have different IDC pinouts and must be
scrambled in the IDC cable in order to be compatible with this demo kit.
Vcc and Gnd MUST be
applied externally here
RxIN LVDS signals
20-pin IDC connector
/PD
60 59
RXOUT27
GND
RXOUT26
GND
RXOUT25
GND
RXOUT24
GND
RXOUT23
GND
RXOUT22
GND
RXOUT21
GND
RXOUT20
GND
RXOUT19
GND
RXOUT18
GND
RXOUT17
GND
RXOUT16
GND
RXOUT15
GND
RXOUT14
GND
RXOUT13
GND
RXOUT12
GND
RXOUT11
GND
RXOUT10
GND
RXOUT9
GND
RXOUT8
GND
RXOUT7
GND
RXOUT6
GND
RXOUT5
GND
RXOUT4
GND
RXOUT3
GND
RXOUT2
GND
RXOUT1
GND
RXOUT0
GND
RXCLKOUT
GND
GND
GND
2 1
J
1
60-pin IDC Connector
1 2
GND
IN0-
IN0+
GND
GND
IN1-
IN1+
GND
GND
IN2-
IN2+
GND
GND
CLK-
CLK+
GND
GND
IN3-
IN3+
GND
19 20
J2
Note: Previous HSL Tx/Rx 8 Bit boards
have different IDC pinouts and must be
scrambled in the IDC cable in order to
be com
p
atible with this demo kit.