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Hardware FAQs

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A.1 Hardware FAQs

1. MSP430F22xx Target Socket Module (MSP-TS430DA38) – Important Information

Due to the large capacitive coupling introduced by the device socket between the adjacent signals

XIN/P2.6 (socket pin 6) and RST/SBWTDIO (socket pin 7), in-system debugging can disturb the

LFXT1 low-frequency crystal oscillator operation (ACLK). This behavior applies only to the Spy-Bi-Wire

(2-wire) JTAG configuration and only to the period while a debug session is active.

Workarounds:

• Use the 4-wire JTAG mode debug configuration instead of the Spy-Bi-Wire (2-wire) JTAG

configuration. This can be achieved by placing jumpers JP4 through JP9 accordingly.

• Use the debugger option "Run Free" that can be selected from the Advanced Run drop-down

menu (at top of Debug View). This prevents the debugger from accessing the MSP430 while the

application is running. Note that, in this mode, a manual halt is required to see if a breakpoint was

hit. See the IDE documentation for more information on this feature.

• Use an external clock source to drive XIN directly.

2. With current interface hardware and software, there is a weakness when adapting target boards

that are powered externally. This leads to an accidental fuse check in the MSP430. This is valid for

PIF and UIF but is mainly seen on UIF. A solution is being developed.

Workarounds:

• Connect RST/NMI pin to JTAG header (pin 11), LPT and USB tools are able to pull the RST line,

which also resets the device internal fuse logic.

• Use the debugger option "Release JTAG On Go" that can be selected from the IDE drop-down

menu. This prevents the debugger from accessing the MSP430 while the application is running.

Note that in this mode, a manual halt is required to see if a breakpoint was hit. See the IDE

documentation for more information on this feature.

• Use an external clock source to drive XIN directly.

3. The 14-conductor cable connecting the FET interface module and the target socket module must not

exceed 8 inches (20 centimeters) in length.

4. The signal assignment on the 14-conductor cable is identical for the parallel port interface and the

USB FET.

5. To utilize the on-chip ADC voltage references, the capacitor must be installed on the target

socket module. See schematic of the target socket module to populate the capacitor according to the

data sheet of the device.

6. To utilize the charge pump on the devices with LCD+ Module, the capacitor must be installed on

the target socket module. See schematic of the target socket module to populate the capacitor

according to the data sheet of the device.

7. Crystals or resonators Q1 and Q2 (if applicable) are not provided on the target socket module.

For MSP430 devices that contain user-selectable loading capacitors, see device and crystal data

sheets for the value of capacitance.

8. Crystals or resonators have no effect upon the operation of the tool and the CCS debugger or

C-SPY (as any required clocking and timing is derived from the internal DCO and FLL).

9. On devices with multiplexed port or JTAG pins, to use these pin in their port capability:

For CCS: "Run Free" (in Run pulldown menu at top of Debug View) must be selected.

For C-SPY: "Release JTAG On Go" must be selected.

10. As an alternative to sharing the JTAG and port pins (on low pin count devices), consider using

an MSP430 device that is a "superset" of the smaller device. A very powerful feature of the

MSP430 is that the family members are code and architecturally compatible, so code developed on

one device (for example, one without shared JTAG and port pins) ports effortlessly to another

(assuming an equivalent set of peripherals).

Frequently Asked Questions and Known Issues SLAU278I–May 2009–Revised May 2012

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