Datasheet

Table 13-4. AES Module Packet Mode Switch Overhead (continued)
TotalCycles needed for first block/and
to finish the last block
New Context
9045
b
/ 45inbound CCM, AES key size is 256
a. Numbers for regular GCM mode (H is precalculated and Y0-encrypted need to be calculated internally using the new IV).
If H needs to be calculated by the core (complete GCM mode), this number needs to be doubled. If Y0-encrypted is not
calculated (forced to zero, such that the hash result is not encrypted) this number is zero.
b. Numbers for regular CCM mode. Dependent on the AAD length it is possible that one additional encryption needs to be
done to finalize the AAD authentication; if the additional operation is required, this number needs to be doubled.
13.4 AES Module Programming Guide
13.4.1 AES Low - Level Programming Models
This section describes the low-level hardware programming sequences for configuring and using
the AES Module.
13.4.1.1 Global Initialization
The following list describes the requirements for initializing the AES and surrounding modules when
AES is used for the first time after a device reset.
1. When reset has completed, enable the AES by setting the R0 bit in the CRC and Cryptographic
Modules Run Mode Clock Gating Control (RCGCCCM), System Control offset 0x674. When
the R0 bit is set in the CRC and Cryptographic Modules Peripheral Ready (PRCCM), System
Control offset 0xA74 register, the AES is powered and ready to be configured.
2. Configure the AES µDMA channels for Context In, Context Out, Data In, and/or Data Out by
programming the appropriate encoding value in the DMA Channel Map Select n (DMACHMAPn)
register in the µDMA module, offset 0x510. For more information on how to program channel
assignments as well as enabling burst and the configured channels, refer to “Micro Direct
Memory Access (μDMA)” on page 686.
3. Execute a software reset by setting the SOFTRESET bit in the AES_SYSCONFIG register. When
reset is complete, the RESETDONE bit reads as 1 in the AES_SYSSTATUS register.
4. If the AES channels are configured in the µDMA, enable the required AES DMA requests by
programming bits [9:5] of the AES_SYSCONFIG register, in addition to the completion interrupts
in the AES DMA Interrupt Mask (AES_DMAIM) register, CCM offset 0x020.
5. Specify the size of the keys by programming the KEY_SIZE bit field in the AES_CTRL register.
6. Load AES Key 1 (AES_KEY1_n) register.
7. Load AES Key 2 (AES_KEY2_n) register if it is used by the configuration mode. Refer to Table
13-6 on page 987 for information regarding which configuration modes require a load to this
register.
8. Configure the AES for the appropriate encryption/decryption mode (see the section called
“Subsequence: Initialize CCM AES Core Mode” on page 980 through the section called
“Subsequence: Initialize CBC AES Core Mode” on page 981).
9. Select encryption or decryption by programming the DIRECTION bit in the AES Control
(AES_CTRL) register, offset 0x050.
979June 18, 2014
Texas Instruments-Production Data
Tiva
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TM4C129ENCPDT Microcontroller