Datasheet

Figure 13-10. AES - GCM Operation
Input buffer
(plain text)
AES core
(encrypt)
Output buffer
(cipher text)
Key register
128
128
256
data_in
data_out
Key in
Encryption
Temporary register
128
128
IV register
IV register
(counter)
127 32 31 0
+
1
32
96
128
32
128
128
x
Authentication Key
128
Authentication
Result
128
128
CCM Operation
Figure 13-11 on page 975 shows one round of a CCM (counter with CBC-MAC) operation for
encryption and decryption. A 32-bit counter is used as IV (as it is for CTR mode). The data is
encrypted in the same way as in CTR mode, by XORing the cryptographic core output with the
input. Immediately after the encryption operation, the plaintext is XORed with the intermediate
authentication result. The XOR result is used as input for a second encryption operation to calculate
the next (intermediate) authentication result.
June 18, 2014974
Texas Instruments-Production Data
Advance Encryption Standard Accelerator (AES)