Datasheet

Figure 13-3. AES - CBC Feedback Mode
Input buffer
(plain text)
AES core
(encrypt)
Output buffer
(cipher text)
Key register
128
128
256
data_in
data_out
Key in
Encryption
IV register
128
128
Input buffer
(cipher text)
AES core
(decrypt)
Output buffer
(plain text)
Key register
128
128
256
data_in
data_out
Key in
Decryption
IV register
128
128
Temporary
register
128
128
128
CTR and ICM Feedback Modes
Figure 13-4 on page 969 shows the counter feedback (CTR/ICM) mode of operation. This operation
encrypts the IV. The output of the cryptographic core (encrypted IV) is XORed with the data, thus
creating the output result.
The IV is built out of two components: a fixed part and a counter part. The counter part is incremented
with each block. The counter width is selectable per context and can be 16, 32, 64, 96, or 128 bits
wide. In this mode, encryption and decryption use the same operation.
Figure 13-4. AES Encryption With CTR/ICM Mode
Input buffer
(plain/cipher text)
AES core
(encrypt)
Output buffer
(cipher/plain text)
Key register
128
128
256
data_in
data_out
Key in
Encryption/Decryption
Temporary register
128
128
IV register
IV register
(counter)
127 32n 32n-1 0
+
1
32n
128-32n
128
32n
969June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller