Datasheet

13.2.1 AES Block Diagram
Figure 13-1 on page 964 shows the AES block diagram. A single-core/dual-interface architecture is
used.
Figure 13-1. AES Block Diagram
AES Core
Mode
Control
FSM
AES
Feedback
Mode
control
Context
Registers
I/O Control FSM/ µDMA Request
Interface
Polynomial
multiplication
HASH block
AES is an efficient implementation of the Rijndael cipher (the AES algorithm) and a 128-bit polynomial
multiplication (referred to here as GHASH, as per the AES-GCM specification). Rijndael is a block
cipher in which each data block is 128 bits. The polynomial multiplication multiplies two 128-bit
vectors using the smallest 128-bit irreducible polynomial, represented by the following 128-bit string:
{0
120
}||10000111. The two implementations are combined into the AES wide-bus engine.
Depending on the availability of context and data, the AES wide-bus engine is automatically triggered
to process the data. The AES wide-bus engine is directly connected to the context and data registers
so that it can immediately start processing when all data is available. The AES wide-bus engine
also interfaces to the I/O Control FSM/µDMA Request Interface.
AES comprises the following major functional blocks:
■ Global control FSM and µDMA interface
■ Register interface module
■ The AES wide-bus engine
The AES wide-bus engine, which is the major top-level component, comprises the following functional
blocks:
■ Mode control FSM: Manages the data flow to and from the AES wide-bus engine and starts each
encryption/decryption operation.
June 18, 2014964
Texas Instruments-Production Data
Advance Encryption Standard Accelerator (AES)