Datasheet

DescriptionResetTypeNameBit/Field
CS1n Read Wait States
This field adds wait states to the data phase of CS1n accesses (the
address phase is not affected).
The effect is to delay the rising edge of RDn/Oen (or the falling edge of
RD). Each wait state encoding adds 2 EPI clock cycles to the access
time. The RDWSM bit in the EPIHB8TIME2 register can decrease the
number of states by 1 EPI clock cycle for greater granularity.
This field is used if the CSBAUD bit is enabled in the EPIHB8CFG2
register. This field is used in conjunction with the EPIBAUD register and
is not applicable in BURST mode.
DescriptionValue
Active RDn is 2 EPI clocks0x0
Active RDn is 4 EPI clocks0x1
Active RDn is 6 EPI clocks0x2
Active RDn is 8 EPI clocks0x3
0x0RWRDWS5:4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved3:2
CS1n Host Bus Sub-Mode
This field determines which Host Bus 8 sub-mode to use for CS1n.
Sub-mode use is determined by the externally connected peripheral or
memory. See Table 11-8 on page 839 for information on how this bit field
affects the operation of the EPI signals.
Note: The CSBAUD bit must be set to enable this CS1n MODE field.
If CSBAUD is clear, all chip-selects use the MODE configuration
defined in the EPIHB8CFG register.
DescriptionValue
ADMUX – AD[7:0]
Data and Address are muxed.
0x0
ADNONMUX – D[7:0]
Data and address are separate.
0x1
reserved0x2-0x3
0x0RWMODE1:0
June 18, 2014892
Texas Instruments-Production Data
External Peripheral Interface (EPI)