Datasheet

Register 3: EPI Main Baud Rate (EPIBAUD2), offset 0x008
The system clock is used internally to the EPI Controller. The baud rate counter can be used to
divide the system clock down to control the speed on the external interface. If the mode selected
emits an external EPI clock, this register defines the EPI clock emitted. If the mode selected does
not use an EPI clock, this register controls the speed of changes on the external interface. Care
must be taken to program this register properly so that the speed of the external bus corresponds
to the speed of the external peripheral and puts acceptable current load on the pins. COUNT0 and
COUNT1 are used in quad chip select mode when different baud rates are selected, page 887 or
page 893. If different baud rates are used, COUNT0 is associated with the address range specified
by CS2n and COUNT1 is associated with the address range specified by CS3n.
The COUNTn field is not a straight divider or count. The EPI Clock on EPI0S31 is related to the
COUNTn field and the system clock as follows:
If COUNTn = 0,
kFreqSystemCloceqEPIClockFr
=
otherwise:
21
2
×
⎟
⎠
⎞
⎜
⎝
⎛
+
⎥
⎦
⎥
⎢
⎣
⎢
=
COUNTn
kFreqSystemCloc
eqEPIClockFr
where the symbol around COUNTn/2 is the floor operator, meaning the largest integer less than or
equal to COUNTn/2.
So, for example, a COUNTn of 0x0001 results in a clock rate of ½(system clock); a COUNTn of 0x0002
or 0x0003 results in a clock rate of ¼(system clock).
EPI Main Baud Rate (EPIBAUD2)
Base 0x400D.0000
Offset 0x008
Type RW, reset 0x0000.0000
16171819202122232425262728293031
COUNT1
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
0123456789101112131415
COUNT0
RWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
CS3n Baud Rate Counter 1
This bit field contains a counter used to divide the system clock by the
count.
A count of 0 means the system clock is unchanged.
This bit field is only valid when quad chip selects are enabled by setting
the CSCFGEXT bit to 1 and the CSCFG field to 0x1 or 0x2. In addition,
the CSBAUD bit must be set in the EPIHBnCFG2 register.
0x0000RWCOUNT131:16
869June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller