Datasheet

Register 1: EPI Configuration (EPICFG), offset 0x000
Important: The MODE field determines which configuration register is accessed for offsets 0x010
and 0x014. Any write to the EPICFG register resets the register contents at offsets
0x010 and 0x014.
The configuration register is used to enable the block, select a mode, and select the basic pin use
(based on the mode). Note that attempting to program an undefined MODE field clears the BLKEN
bit and disables the EPI controller.
EPI Configuration (EPICFG)
Base 0x400D.0000
Offset 0x000
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MODEBLKENreservedINTDIVreserved
RWRWRWRWRWRORORORWROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:9
Integer Clock Divider Enable
DescriptionValue
EPIBAUD register values create formula clock divide.0
EPIBAUD register values create integer clock divide.1
0RWINTDIV8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved7:5
Block Enable
DescriptionValue
The EPI controller is disabled.0
The EPI controller is enabled.1
0RWBLKEN4
865June 18, 2014
Texas Instruments-Production Data
Tiva
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TM4C129ENCPDT Microcontroller