Datasheet

Support for up to 512 Mb PSRAM in quad chip select mode, with dedicated configuration
register read and write enable.
Support of both muxed and de-muxed address and data
Access to a range of devices supporting the non-address FIFO x8 and x16 interface variant,
with support for external FIFO (XFIFO) EMPTY and FULL signals
Speed controlled, with read and write data wait-state counters
Support for read/write burst mode to Host Bus
Multiple chip select modes including single, dual, and quad chip selects, with and without
ALE
External iRDY signal provided for stall capability of reads and writes
Manual chip-enable (or use extra address pins)
General-Purpose mode
Wide parallel interfaces for fast communications with CPLDs and FPGAs
Data widths up to 32 bits
Data rates up to 150 MB/second
Optional "address" sizes from 4 bits to 20 bits
Optional clock output, read/write strobes, framing (with counter-based size), and clock-enable
input
General parallel GPIO
1 to 32 bits, FIFOed with speed control
Useful for custom peripherals or for digital data acquisition and actuator controls
11.1 EPI Block Diagram
Figure 11-1 on page 825 provides a block diagram of a TM4C129ENCPDT EPI module.
June 18, 2014824
Texas Instruments-Production Data
External Peripheral Interface (EPI)