Datasheet

Register 31: GPIO Peripheral Configuration (GPIOPC), offset 0xFC4
This GPIOPC register controls the extended drive modes of the GPIO and must be configured before
the GPIODRnR registers in order for extended drive mode to take effect. When the EDE bit in
GPIOPP register is set and the EDMn bit field is non-zero, the GPIODRnR registers do not drive
their default value, but instead output an incremental drive strength, which has an additive effect.
This allows for more drive strength possibilities. When the EDE bit is set and the EDMn bit field is
non-zero, the 2 mA driver is always enabled. Any bits enabled in the GPIODR4R register will add
an additional 2 mA; any bits set in the GPIODR8R add an extra 4 mA of drive. The GPIODR12R
register is only valid when the EDMn value is 0x3. For this encoding, setting a bit in the GPIODR12R
register adds 4 mA of drive to the already existing 8 mA, for a 12 mA drive strength. Table
10-3 on page 761 shows the drive capability options. If EDMn is 0x00, then the GPIODR2R,
GPIODR4R, and GPIODR8R function as stated in their default register description.
Table 10-13. GPIO Drive Strength Options
Drive (mA)GPIODR2R (2mA)GPIODR4R
(+2mA)
GPIODR8R
(+4mA)
GPIODR12R
(+4mA)
EDMn
(GPIOPC)
EDE
(GPIOPP)
2100
N/A0x0X 4010
8001
2N/A00
N/A0x11
4N/A10
6N/A01
8N/A11
2N/A000
0x31
4N/A100
6N/A010
8N/A110
10N/A011
12N/A111
N/AN/AN/A01
N/AN/AN/AN/AN/A0x21
June 18, 2014808
Texas Instruments-Production Data
General-Purpose Input/Outputs (GPIOs)