Datasheet

15.1.2 Power Management .................................................................................................. 1046
15.1.3 Reset Management ................................................................................................... 1046
15.1.4 µDMA and Interrupt Requests .................................................................................... 1046
15.1.5 Operation Description ................................................................................................ 1047
15.1.6 SHA/MD5 Performance Information ............................................................................ 1053
15.1.7 SHA/MD5 Programming Guide ................................................................................... 1054
15.2 SHA/MD5 Register Map ............................................................................................. 1058
15.3 SHA/MD5 Register Descriptions ................................................................................. 1060
15.4 SHA/MD5 µDMA Control Register Descriptions (Encryption Control Offset) ................... 1074
16 General-Purpose Timers .................................................................................... 1079
16.1 Block Diagram ........................................................................................................... 1080
16.2 Signal Description ..................................................................................................... 1081
16.3 Functional Description ............................................................................................... 1082
16.3.1 GPTM Reset Conditions ............................................................................................ 1083
16.3.2 Timer Clock Source ................................................................................................... 1083
16.3.3 Timer Modes ............................................................................................................. 1083
16.3.4 Wait-for-Trigger Mode ................................................................................................ 1092
16.3.5 Synchronizing GP Timer Blocks .................................................................................. 1093
16.3.6 DMA Operation ......................................................................................................... 1094
16.3.7 ADC Operation .......................................................................................................... 1094
16.3.8 Accessing Concatenated 16/32-Bit GPTM Register Values .......................................... 1094
16.4 Initialization and Configuration .................................................................................... 1095
16.4.1 One-Shot/Periodic Timer Mode .................................................................................. 1095
16.4.2 Real-Time Clock (RTC) Mode ..................................................................................... 1096
16.4.3 Input Edge-Count Mode ............................................................................................. 1096
16.4.4 Input Edge Time Mode ............................................................................................... 1097
16.4.5 PWM Mode ............................................................................................................... 1097
16.5 Register Map ............................................................................................................ 1098
16.6 Register Descriptions ................................................................................................. 1099
17 Watchdog Timers ............................................................................................... 1152
17.1 Block Diagram ........................................................................................................... 1153
17.2 Functional Description ............................................................................................... 1153
17.2.1 Register Access Timing ............................................................................................. 1154
17.3 Initialization and Configuration .................................................................................... 1154
17.4 Register Map ............................................................................................................ 1154
17.5 Register Descriptions ................................................................................................. 1155
18 Analog-to-Digital Converter (ADC) ................................................................... 1177
18.1 Block Diagram ........................................................................................................... 1178
18.2 Signal Description ..................................................................................................... 1179
18.3 Functional Description ............................................................................................... 1180
18.3.1 Sample Sequencers .................................................................................................. 1180
18.3.2 Module Control .......................................................................................................... 1181
18.3.3 Hardware Sample Averaging Circuit ........................................................................... 1186
18.3.4 Analog-to-Digital Converter ........................................................................................ 1187
18.3.5 Differential Sampling .................................................................................................. 1189
18.3.6 Internal Temperature Sensor ...................................................................................... 1191
18.3.7 Digital Comparator Unit .............................................................................................. 1192
18.4 Initialization and Configuration .................................................................................... 1196
June 18, 20148
Texas Instruments-Production Data
Table of Contents