Datasheet
– High-speed mode (3.33 Mbps)
■ Glitch suppression
■ SMBus support through software
– Clock low timeout interrupt
– Dual slave address capability
– Quick command capability
■ Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
– Slave generates interrupts when data has been transferred or requested by a master or when
a START or STOP condition is detected
■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Ability to execute single data transfers or burst data transfers using the RX and TX FIFOs in
the I
2
C
1.3.8.6 QSSI (see page 1350)
Quad Synchronous Serial Interface (QSSI) is a bi-directional communications interface that converts
data between parallel and serial. The QSSI module performs serial-to-parallel conversion on data
received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral
device. The QSSI module can be configured as either a master or slave device. As a slave device,
the QSSI module can also be configured to disable its output, which allows a master device to be
coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs.
The QSSI module also includes a programmable bit rate clock divider and prescaler to generate
the output serial clock derived from the QSSI module's input clock. Bit rates are generated based
on the input clock and the maximum bit rate is determined by the connected peripheral.
The TM4C129ENCPDT microcontroller includes four QSSI modules with the following features:
■ Four QSSI channels with Advanced, Bi- and Quad-SSI functionality
■ Programmable interface operation for Freescale SPI or Texas Instruments synchronous serial
interfaces in Legacy Mode. Support for Freescale interface in Bi- and Quad-SSI mode.
■ Master or slave operation
■ Programmable clock bit rate and prescaler
■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
■ Programmable data frame size from 4 to 16 bits
June 18, 201472
Texas Instruments-Production Data
Architectural Overview