Datasheet

Table 9-13. μDMA Register Map (continued)
See
page
DescriptionResetTypeNameOffset
725DMA Channel Useburst Set0x0000.0000RWDMAUSEBURSTSET0x018
726DMA Channel Useburst Clear-WODMAUSEBURSTCLR0x01C
727DMA Channel Request Mask Set0x0000.0000RWDMAREQMASKSET0x020
728DMA Channel Request Mask Clear-WODMAREQMASKCLR0x024
729DMA Channel Enable Set0x0000.0000RWDMAENASET0x028
730DMA Channel Enable Clear-WODMAENACLR0x02C
731DMA Channel Primary Alternate Set0x0000.0000RWDMAALTSET0x030
732DMA Channel Primary Alternate Clear-WODMAALTCLR0x034
733DMA Channel Priority Set0x0000.0000RWDMAPRIOSET0x038
734DMA Channel Priority Clear-WODMAPRIOCLR0x03C
735DMA Bus Error Clear0x0000.0000RWDMAERRCLR0x04C
736DMA Channel Assignment0x0000.0000RWDMACHASGN0x500
737DMA Channel Map Select 00x0000.0000RWDMACHMAP00x510
738DMA Channel Map Select 10x0000.0000RWDMACHMAP10x514
739DMA Channel Map Select 20x0000.0000RWDMACHMAP20x518
740DMA Channel Map Select 30x0000.0000RWDMACHMAP30x51C
745DMA Peripheral Identification 40x0000.0004RODMAPeriphID40xFD0
741DMA Peripheral Identification 00x0000.0030RODMAPeriphID00xFE0
742DMA Peripheral Identification 10x0000.00B2RODMAPeriphID10xFE4
743DMA Peripheral Identification 20x0000.000BRODMAPeriphID20xFE8
744DMA Peripheral Identification 30x0000.0000RODMAPeriphID30xFEC
746DMA PrimeCell Identification 00x0000.000DRODMAPCellID00xFF0
747DMA PrimeCell Identification 10x0000.00F0RODMAPCellID10xFF4
748DMA PrimeCell Identification 20x0000.0005RODMAPCellID20xFF8
749DMA PrimeCell Identification 30x0000.00B1RODMAPCellID30xFFC
9.5 μDMA Channel Control Structure
The μDMA Channel Control Structure holds the transfer settings for a μDMA channel. Each channel
has two control structures, which are located in a table in system memory. Refer to “Channel
Configuration” on page 691 for an explanation of the Channel Control Table and the Channel Control
Structure.
The channel control structure is one entry in the channel control table. Each channel has a primary
and alternate structure. The primary control structures are located at offsets 0x0, 0x10, 0x20 and
so on. The alternate control structures are located at offsets 0x200, 0x210, 0x220, and so on.
June 18, 2014710
Texas Instruments-Production Data
Micro Direct Memory Access (μDMA)