Datasheet

11.4.2 SDRAM Mode ............................................................................................................. 830
11.4.3 Host Bus Mode ........................................................................................................... 834
11.4.4 General-Purpose Mode ............................................................................................... 855
11.5 Register Map .............................................................................................................. 862
11.6 Register Descriptions .................................................................................................. 864
12 Cyclical Redundancy Check (CRC) .................................................................... 954
12.1 Functional Description ................................................................................................. 954
12.1.1 CRC Support .............................................................................................................. 954
12.2 Initialization and Configuration ..................................................................................... 956
12.2.1 CRC Initialization and Configuration ............................................................................. 956
12.3 Register Map .............................................................................................................. 957
12.4 CRC Module Register Descriptions .............................................................................. 957
13 Advance Encryption Standard Accelerator (AES) ............................................ 963
13.1 AES Overview ............................................................................................................. 963
13.2 AES Functional Description .......................................................................................... 963
13.2.1 AES Block Diagram ..................................................................................................... 964
13.2.2 AES Algorithm ............................................................................................................ 967
13.2.3 AES Operating Modes ................................................................................................. 968
13.2.4 AES Software Reset .................................................................................................... 976
13.2.5 Power Management .................................................................................................... 976
13.2.6 Hardware Requests ..................................................................................................... 976
13.3 AES Performance Information ...................................................................................... 977
13.4 AES Module Programming Guide ................................................................................. 979
13.4.1 AES Low - Level Programming Models ......................................................................... 979
13.5 Register Map .............................................................................................................. 984
13.6 AES Register Descriptions ........................................................................................... 986
13.7 AES µDMA Interrupt Register Descriptions (CCM Offset) ............................................. 1008
14 Data Encryption Standard Accelerator (DES) ................................................. 1015
14.1 DES Functional Description ........................................................................................ 1015
14.2 DES Block Diagram ................................................................................................... 1016
14.2.1 µDMA Control ........................................................................................................... 1016
14.2.2 Interrupt Control ........................................................................................................ 1017
14.2.3 Register Interface ...................................................................................................... 1017
14.2.4 DES Engine .............................................................................................................. 1017
14.3 Software Reset ......................................................................................................... 1018
14.4 DES Supported Modes of Operation ........................................................................... 1018
14.4.1 ECB Feedback Mode ................................................................................................. 1018
14.5 DES Module Programming Guide -Low Level Programming Models ............................. 1020
14.5.1 Surrounding Modules Global Initialization .................................................................... 1020
14.5.2 Operational Modes Configuration ............................................................................... 1021
14.5.3 DES Events Servicing ................................................................................................ 1023
14.6 Register Map ............................................................................................................ 1024
14.7 DES Register Description .......................................................................................... 1025
14.8 DES µDMA Interrupt Register Descriptions (CCM Offset) ............................................. 1039
15 SHA/MD5 Accelerator ........................................................................................ 1044
15.1 SHA/MD5 Functional Description ................................................................................ 1044
15.1.1 SHA/MD5 Block Diagram ........................................................................................... 1044
7June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller