Datasheet

Promiscuous mode support
Processor offloading
Programmable insertion (TX) or deletion (RX) of preamble and start-of-frame data
Programmable generation (TX) or deletion (RX) of CRC and pad data
IP header and hardware checksum checking (IPv4, IPv6, TCP/UDP/ICMP)
Highly configurable
LED activity selection
Supports network statistics with RMON/MIB counters
Supports Magic Packet and wakeup frames
Efficient transfers using integrated Direct Memory Access (DMA)
Dual-buffer (ring) or linked-list (chained) descriptors
Round-robin or fixed priority arbitration between TX/RX
Descriptors support up to 8 kB transfer blocks size
Programmable interrupts for flexible system implementation
Physical media manipulation
MDI/MDI-X cross-over support
Register-programmable transmit amplitude
Automatic polarity correction and 10BASE-T signal reception
1.3.8.2 Controller Area Network (CAN) (see page 1480)
Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy
environments and can utilize a differential balanced line like RS-485 or twisted-pair wire. Originally
created for automotive purposes, it is now used in many embedded control applications (for example,
industrial or medical). Bit rates up to 1 Mbps are possible at network lengths below 40 meters.
Decreased bit rates allow longer network distances (for example, 125 Kbps at 500m).
A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis
of the identifier received whether it should process the message. The identifier also determines the
priority that the message enjoys in competition for bus access. Each CAN message can transmit
from 0 to 8 bytes of user information.
The TM4C129ENCPDT microcontroller includes two CAN units with the following features:
CAN protocol version 2.0 part A/B
Bit rates up to 1 Mbps
32 message objects with individual identifier masks
June 18, 201468
Texas Instruments-Production Data
Architectural Overview