Datasheet
8.3 Register Map .............................................................................................................. 629
8.4 Internal Memory Register Descriptions (Internal Memory Control Offset) ......................... 632
8.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 658
8.6 Memory Register Descriptions (System Control Offset) .................................................. 675
9 Micro Direct Memory Access (μDMA) ................................................................ 686
9.1 Block Diagram ............................................................................................................ 687
9.2 Functional Description ................................................................................................. 687
9.2.1 Channel Assignments .................................................................................................. 688
9.2.2 Priority ........................................................................................................................ 689
9.2.3 Arbitration Size ............................................................................................................ 690
9.2.4 Request Types ............................................................................................................ 690
9.2.5 Channel Configuration ................................................................................................. 691
9.2.6 Transfer Modes ........................................................................................................... 693
9.2.7 Transfer Size and Increment ........................................................................................ 701
9.2.8 Peripheral Interface ..................................................................................................... 701
9.2.9 Software Request ........................................................................................................ 702
9.2.10 Interrupts and Errors .................................................................................................... 702
9.3 Initialization and Configuration ..................................................................................... 702
9.3.1 Module Initialization ..................................................................................................... 702
9.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 703
9.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 704
9.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 706
9.3.5 Configuring Channel Assignments ................................................................................ 709
9.4 Register Map .............................................................................................................. 709
9.5 μDMA Channel Control Structure ................................................................................. 710
9.6 μDMA Register Descriptions ........................................................................................ 717
10 General-Purpose Input/Outputs (GPIOs) ........................................................... 750
10.1 Signal Description ....................................................................................................... 751
10.2 Pad Capabilities .......................................................................................................... 754
10.3 Functional Description ................................................................................................. 755
10.3.1 Data Control ............................................................................................................... 756
10.3.2 Interrupt Control .......................................................................................................... 758
10.3.3 Mode Control .............................................................................................................. 759
10.3.4 Commit Control ........................................................................................................... 760
10.3.5 Pad Control ................................................................................................................. 760
10.3.6 Identification ............................................................................................................... 761
10.4 Initialization and Configuration ..................................................................................... 761
10.5 Register Map .............................................................................................................. 763
10.6 Register Descriptions .................................................................................................. 766
11 External Peripheral Interface (EPI) ..................................................................... 823
11.1 EPI Block Diagram ...................................................................................................... 824
11.2 Signal Description ....................................................................................................... 825
11.3 Functional Description ................................................................................................. 826
11.3.1 Master Access to EPI .................................................................................................. 827
11.3.2 Non-Blocking Reads .................................................................................................... 827
11.3.3 DMA Operation ........................................................................................................... 828
11.4 Initialization and Configuration ..................................................................................... 829
11.4.1 EPI Interface Options .................................................................................................. 830
June 18, 20146
Texas Instruments-Production Data
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