Datasheet

Register 142: CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating
Control (DCGCCCM), offset 0x874
The DCGCCCM register provides software the capability to enable and disable the CRC, AES,
DES, and SHA/MD5 modules in deep-sleep mode. When enabled, the modules are provided a
clock. When disabled, the clock is disabled to save power.
Important: This register should be used to control the clocking for the CRC, AES, DES, and SHA/MD
modules.
CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control (DCGCCCM)
Base 0x400F.E000
Offset 0x874
Type RW, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
D0reserved
RWROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:1
CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control
DescriptionValue
The CRC, AES, DES, and SHA/MD5 modules are disabled in
deep-sleep mode.
0
Enable and provide a clock to the CRC, AES, DES, and
SHA/MD5 modules in deep-sleep mode.
1
0RWD00
June 18, 2014456
Texas Instruments-Production Data
System Control