Datasheet

Register 7: I
2
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 .......................................... 1445
Register 8: I
2
C Master Interrupt Clear (I2CMICR), offset 0x01C ....................................................... 1448
Register 9: I
2
C Master Configuration (I2CMCR), offset 0x020 .......................................................... 1450
Register 10: I
2
C Master Clock Low Timeout Count (I2CMCLKOCNT), offset 0x024 ............................. 1451
Register 11: I
2
C Master Bus Monitor (I2CMBMON), offset 0x02C ....................................................... 1452
Register 12: I
2
C Master Burst Length (I2CMBLEN), offset 0x030 ....................................................... 1453
Register 13: I
2
C Master Burst Count (I2CMBCNT), offset 0x034 ........................................................ 1454
Register 14: I
2
C Slave Own Address (I2CSOAR), offset 0x800 .......................................................... 1455
Register 15: I
2
C Slave Control/Status (I2CSCSR), offset 0x804 ......................................................... 1456
Register 16: I
2
C Slave Data (I2CSDR), offset 0x808 ......................................................................... 1459
Register 17: I
2
C Slave Interrupt Mask (I2CSIMR), offset 0x80C ......................................................... 1460
Register 18: I
2
C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................. 1462
Register 19: I
2
C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 ............................................ 1465
Register 20: I
2
C Slave Interrupt Clear (I2CSICR), offset 0x818 .......................................................... 1468
Register 21: I
2
C Slave Own Address 2 (I2CSOAR2), offset 0x81C ..................................................... 1470
Register 22: I
2
C Slave ACK Control (I2CSACKCTL), offset 0x820 ...................................................... 1471
Register 23: I
2
C FIFO Data (I2CFIFODATA), offset 0xF00 ................................................................. 1472
Register 24: I
2
C FIFO Control (I2CFIFOCTL), offset 0xF04 ............................................................... 1474
Register 25: I
2
C FIFO Status (I2CFIFOSTATUS), offset 0xF08 .......................................................... 1476
Register 26: I
2
C Peripheral Properties (I2CPP), offset 0xFC0 ............................................................ 1478
Register 27: I
2
C Peripheral Configuration (I2CPC), offset 0xFC4 ....................................................... 1479
Controller Area Network (CAN) Module ................................................................................... 1480
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................ 1502
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................. 1504
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................. 1507
Register 4: CAN Bit Timing (CANBIT), offset 0x00C ........................................................................ 1508
Register 5: CAN Interrupt (CANINT), offset 0x010 ........................................................................... 1509
Register 6: CAN Test (CANTST), offset 0x014 ................................................................................ 1510
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ..................................... 1512
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 .............................................. 1513
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 .............................................. 1513
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 ................................................ 1514
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 ................................................ 1514
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 .............................................................. 1517
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 .............................................................. 1517
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C .............................................................. 1518
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C .............................................................. 1518
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ....................................................... 1520
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ....................................................... 1520
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ....................................................... 1521
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ....................................................... 1521
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 ................................................ 1523
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 ................................................ 1523
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ............................................................... 1526
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................ 1526
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................ 1526
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................ 1526
43June 18, 2014
Texas Instruments-Production Data
Tiva
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TM4C129ENCPDT Microcontroller