Datasheet

Register 15: UART 9-Bit Self Address (UART9BITADDR), offset 0x0A4 ............................................. 1333
Register 16: UART 9-Bit Self Address Mask (UART9BITAMASK), offset 0x0A8 .................................. 1334
Register 17: UART Peripheral Properties (UARTPP), offset 0xFC0 .................................................... 1335
Register 18: UART Clock Configuration (UARTCC), offset 0xFC8 ...................................................... 1337
Register 19: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ................................... 1338
Register 20: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ................................... 1339
Register 21: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ................................... 1340
Register 22: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ................................... 1341
Register 23: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 .................................... 1342
Register 24: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 .................................... 1343
Register 25: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 .................................... 1344
Register 26: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ................................... 1345
Register 27: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ...................................... 1346
Register 28: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ...................................... 1347
Register 29: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ...................................... 1348
Register 30: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ...................................... 1349
Quad Synchronous Serial Interface (QSSI) ............................................................................. 1350
Register 1: QSSI Control 0 (SSICR0), offset 0x000 ......................................................................... 1369
Register 2: QSSI Control 1 (SSICR1), offset 0x004 ......................................................................... 1371
Register 3: QSSI Data (SSIDR), offset 0x008 ................................................................................. 1373
Register 4: QSSI Status (SSISR), offset 0x00C ............................................................................... 1374
Register 5: QSSI Clock Prescale (SSICPSR), offset 0x010 .............................................................. 1376
Register 6: QSSI Interrupt Mask (SSIIM), offset 0x014 .................................................................... 1377
Register 7: QSSI Raw Interrupt Status (SSIRIS), offset 0x018 ......................................................... 1379
Register 8: QSSI Masked Interrupt Status (SSIMIS), offset 0x01C ................................................... 1381
Register 9: QSSI Interrupt Clear (SSIICR), offset 0x020 .................................................................. 1383
Register 10: QSSI DMA Control (SSIDMACTL), offset 0x024 ............................................................. 1384
Register 11: QSSI Peripheral Properties (SSIPP), offset 0xFC0 ......................................................... 1385
Register 12: QSSI Clock Configuration (SSICC), offset 0xFC8 ........................................................... 1386
Register 13: QSSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ........................................ 1387
Register 14: QSSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ........................................ 1388
Register 15: QSSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ........................................ 1389
Register 16: QSSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ........................................ 1390
Register 17: QSSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ........................................ 1391
Register 18: QSSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ........................................ 1392
Register 19: QSSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ........................................ 1393
Register 20: QSSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ........................................ 1394
Register 21: QSSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ........................................... 1395
Register 22: QSSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ........................................... 1396
Register 23: QSSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ........................................... 1397
Register 24: QSSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC .......................................... 1398
Inter-Integrated Circuit (I
2
C) Interface ...................................................................................... 1399
Register 1: I
2
C Master Slave Address (I2CMSA), offset 0x000 ......................................................... 1426
Register 2: I
2
C Master Control/Status (I2CMCS), offset 0x004 ......................................................... 1427
Register 3: I
2
C Master Data (I2CMDR), offset 0x008 ....................................................................... 1436
Register 4: I
2
C Master Timer Period (I2CMTPR), offset 0x00C ......................................................... 1437
Register 5: I
2
C Master Interrupt Mask (I2CMIMR), offset 0x010 ....................................................... 1439
Register 6: I
2
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ............................................... 1442
June 18, 201442
Texas Instruments-Production Data
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