Datasheet
Register 37: ADC Sample Sequence Extended Input Multiplexer Select 1 (ADCSSEMUX1), offset
0x078 .......................................................................................................................... 1261
Register 38: ADC Sample Sequence Extended Input Multiplexer Select 2 (ADCSSEMUX2), offset 0x098
.................................................................................................................................... 1261
Register 39: ADC Sample Sequence 1 Sample and Hold Time (ADCSSTSH1), offset 0x07C .............. 1263
Register 40: ADC Sample Sequence 2 Sample and Hold Time (ADCSSTSH2), offset 0x09C .............. 1263
Register 41: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............. 1265
Register 42: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ...................................... 1266
Register 43: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 .................................... 1268
Register 44: ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 ............ 1269
Register 45: ADC Sample Sequence Extended Input Multiplexer Select 3 (ADCSSEMUX3), offset
0x0B8 ......................................................................................................................... 1270
Register 46: ADC Sample Sequence 3 Sample and Hold Time (ADCSSTSH3), offset 0x0BC .............. 1271
Register 47: ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ................... 1272
Register 48: ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ..................................... 1277
Register 49: ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ..................................... 1277
Register 50: ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ..................................... 1277
Register 51: ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C .................................... 1277
Register 52: ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ..................................... 1277
Register 53: ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ..................................... 1277
Register 54: ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ..................................... 1277
Register 55: ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C .................................... 1277
Register 56: ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ..................................... 1280
Register 57: ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ..................................... 1280
Register 58: ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ..................................... 1280
Register 59: ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C .................................... 1280
Register 60: ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ..................................... 1280
Register 61: ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ..................................... 1280
Register 62: ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ..................................... 1280
Register 63: ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C .................................... 1280
Register 64: ADC Peripheral Properties (ADCPP), offset 0xFC0 ........................................................ 1281
Register 65: ADC Peripheral Configuration (ADCPC), offset 0xFC4 ................................................... 1283
Register 66: ADC Clock Configuration (ADCCC), offset 0xFC8 .......................................................... 1284
Universal Asynchronous Receivers/Transmitters (UARTs) ................................................... 1285
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................. 1299
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ......................... 1301
Register 3: UART Flag (UARTFR), offset 0x018 .............................................................................. 1304
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................ 1307
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 .......................................... 1308
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ..................................... 1309
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................. 1310
Register 8: UART Control (UARTCTL), offset 0x030 ........................................................................ 1312
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 .......................................... 1316
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................ 1318
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C .................................................... 1322
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ............................................... 1326
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 .............................................................. 1330
Register 14: UART DMA Control (UARTDMACTL), offset 0x048 ........................................................ 1332
41June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller