Datasheet
Register 38: SHA System Status (SHA_SYSSTATUS), offset 0x114 ................................................... 1071
Register 39: SHA Interrupt Status (SHA_IRQSTATUS), offset 0x118 .................................................. 1072
Register 40: SHA Interrupt Enable (SHA_IRQENABLE), offset 0x11C ................................................ 1073
Register 41: SHA DMA Interrupt Mask (SHA_DMAIM), offset 0x010 .................................................. 1075
Register 42: SHA DMA Raw Interrupt Status (SHA_DMARIS), offset 0x014 ....................................... 1076
Register 43: SHA DMA Masked Interrupt Status (SHA_DMAMIS), offset 0x018 .................................. 1077
Register 44: SHA DMA Interrupt Clear (SHA_DMAIC), offset 0x01C .................................................. 1078
General-Purpose Timers ........................................................................................................... 1079
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 ............................................................. 1100
Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 ......................................................... 1101
Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008 ......................................................... 1106
Register 4: GPTM Control (GPTMCTL), offset 0x00C ...................................................................... 1110
Register 5: GPTM Synchronize (GPTMSYNC), offset 0x010 ............................................................ 1114
Register 6: GPTM Interrupt Mask (GPTMIMR), offset 0x018 ............................................................ 1117
Register 7: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ................................................... 1120
Register 8: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 .............................................. 1123
Register 9: GPTM Interrupt Clear (GPTMICR), offset 0x024 ............................................................ 1126
Register 10: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 .............................................. 1128
Register 11: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C .............................................. 1129
Register 12: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 ................................................ 1130
Register 13: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................ 1131
Register 14: GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ..................................................... 1132
Register 15: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ..................................................... 1133
Register 16: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ......................................... 1134
Register 17: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ......................................... 1135
Register 18: GPTM Timer A (GPTMTAR), offset 0x048 ..................................................................... 1136
Register 19: GPTM Timer B (GPTMTBR), offset 0x04C ..................................................................... 1137
Register 20: GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................. 1138
Register 21: GPTM Timer B Value (GPTMTBV), offset 0x054 ............................................................ 1139
Register 22: GPTM RTC Predivide (GPTMRTCPD), offset 0x058 ...................................................... 1140
Register 23: GPTM Timer A Prescale Snapshot (GPTMTAPS), offset 0x05C ...................................... 1141
Register 24: GPTM Timer B Prescale Snapshot (GPTMTBPS), offset 0x060 ...................................... 1142
Register 25: GPTM DMA Event (GPTMDMAEV), offset 0x06C .......................................................... 1143
Register 26: GPTM ADC Event (GPTMADCEV), offset 0x070 ........................................................... 1146
Register 27: GPTM Peripheral Properties (GPTMPP), offset 0xFC0 ................................................... 1149
Register 28: GPTM Clock Configuration (GPTMCC), offset 0xFC8 ..................................................... 1151
Watchdog Timers ....................................................................................................................... 1152
Register 1: Watchdog Load (WDTLOAD), offset 0x000 .................................................................... 1156
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................. 1157
Register 3: Watchdog Control (WDTCTL), offset 0x008 ................................................................... 1158
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C ......................................................... 1160
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ................................................ 1161
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ........................................... 1162
Register 7: Watchdog Test (WDTTEST), offset 0x418 ...................................................................... 1163
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 .................................................................... 1164
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ............................... 1165
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ............................... 1166
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ............................... 1167
39June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller