Datasheet

Register 8: AES Key 2_1 (AES_KEY2_1), offset 0x01C .................................................................... 987
Register 9: AES Key 1_6 (AES_KEY1_6), offset 0x020 ..................................................................... 987
Register 10: AES Key 1_7 (AES_KEY1_7), offset 0x024 ..................................................................... 987
Register 11: AES Key 1_4 (AES_KEY1_4), offset 0x028 ..................................................................... 987
Register 12: AES Key 1_5 (AES_KEY1_5), offset 0x02C .................................................................... 987
Register 13: AES Key 1_2 (AES_KEY1_2), offset 0x030 ..................................................................... 987
Register 14: AES Key 1_3 (AES_KEY1_3), offset 0x034 ..................................................................... 987
Register 15: AES Key 1_0 (AES_KEY1_0), offset 0x038 ..................................................................... 987
Register 16: AES Key 1_1 (AES_KEY1_1), offset 0x03C .................................................................... 987
Register 17: AES Initialization Vector Input 0 (AES_IV_IN_0), offset 0x040 .......................................... 989
Register 18: AES Initialization Vector Input 1 (AES_IV_IN_1), offset 0x044 .......................................... 989
Register 19: AES Initialization Vector Input 2 (AES_IV_IN_2), offset 0x048 .......................................... 989
Register 20: AES Initialization Vector Input 3 (AES_IV_IN_3), offset 0x04C .......................................... 989
Register 21: AES Control (AES_CTRL), offset 0x050 .......................................................................... 990
Register 22: AES Crypto Data Length 0 (AES_C_LENGTH_0), offset 0x054 ........................................ 995
Register 23: AES Crypto Data Length 1 (AES_C_LENGTH_1), offset 0x058 ........................................ 995
Register 24: AES Authentication Data Length (AES_AUTH_LENGTH), offset 0x05C ............................ 996
Register 25: AES Data RW Plaintext/Ciphertext 0 (AES_DATA_IN_0), offset 0x060 .............................. 997
Register 26: AES Data RW Plaintext/Ciphertext 1 (AES_DATA_IN_1), offset 0x064 .............................. 997
Register 27: AES Data RW Plaintext/Ciphertext 2 (AES_DATA_IN_2), offset 0x068 .............................. 997
Register 28: AES Data RW Plaintext/Ciphertext 3 (AES_DATA_IN_3), offset 0x06C ............................. 997
Register 29: AES Hash Tag Out 0 (AES_TAG_OUT_0), offset 0x070 ................................................... 998
Register 30: AES Hash Tag Out 1 (AES_TAG_OUT_1), offset 0x074 ................................................... 998
Register 31: AES Hash Tag Out 2 (AES_TAG_OUT_2), offset 0x078 ................................................... 998
Register 32: AES Hash Tag Out 3 (AES_TAG_OUT_3), offset 0x07C .................................................. 998
Register 33: AES IP Revision Identifier (AES_REVISION), offset 0x080 ............................................... 999
Register 34: AES System Configuration (AES_SYSCONFIG), offset 0x084 ........................................ 1000
Register 35: AES System Status (AES_SYSSTATUS), offset 0x088 ................................................... 1003
Register 36: AES Interrupt Status (AES_IRQSTATUS), offset 0x08C .................................................. 1004
Register 37: AES Interrupt Enable (AES_IRQENABLE), offset 0x090 ................................................. 1006
Register 38: AES Dirty Bits (AES_DIRTYBITS), offset 0x094 ............................................................. 1008
Register 39: AES DMA Interrupt Mask (AES_DMAIM), offset 0x020 ................................................... 1009
Register 40: AES DMA Raw Interrupt Status (AES_DMARIS), offset 0x024 ........................................ 1011
Register 41: AES DMA Masked Interrupt Status (AES_DMAMIS), offset 0x028 .................................. 1013
Register 42: AES DMA Interrupt Clear (AES_DMAIC), offset 0x02C ................................................... 1014
Data Encryption Standard Accelerator (DES) ......................................................................... 1015
Register 1: DES Key 3 LSW for 192-Bit Key (DES_KEY3_L), offset 0x000 ....................................... 1026
Register 2: DES Key 3 MSW for 192-Bit Key (DES_KEY3_H), offset 0x004 ...................................... 1026
Register 3: DES Key 2 LSW for 128-Bit Key (DES_KEY2_L), offset 0x008 ....................................... 1026
Register 4: DES Key 2 MSW for 128-Bit Key (DES_KEY2_H), offset 0x00C ..................................... 1026
Register 5: DES Key 1 LSW for 64-Bit Key (DES_KEY1_L), offset 0x010 ......................................... 1026
Register 6: DES Key 1 MSW for 64-Bit Key (DES_KEY1_H), offset 0x014 ........................................ 1026
Register 7: DES Initialization Vector (DES_IV_L), offset 0x018 ........................................................ 1027
Register 8: DES Initialization Vector (DES_IV_H), offset 0x01C ....................................................... 1028
Register 9: DES Control (DES_CTRL), offset 0x020 ........................................................................ 1029
Register 10: DES Cryptographic Data Length (DES_LENGTH), offset 0x024 ...................................... 1030
Register 11: DES LSW Data RW (DES_DATA_L), offset 0x028 ......................................................... 1031
Register 12: DES MSW Data RW (DES_DATA_H), offset 0x02C ....................................................... 1032
37June 18, 2014
Texas Instruments-Production Data
Tiva
TM4C129ENCPDT Microcontroller