Datasheet
Table of Contents
Revision History ............................................................................................................................. 49
About This Document .................................................................................................................... 52
Audience .............................................................................................................................................. 52
About This Manual ................................................................................................................................ 52
Related Documents ............................................................................................................................... 52
Documentation Conventions .................................................................................................................. 53
1 Architectural Overview .......................................................................................... 55
1.1 Tiva™ C Series Overview .............................................................................................. 55
1.2 TM4C129ENCPDT Microcontroller Overview .................................................................. 56
1.3 TM4C129ENCPDT Microcontroller Features ................................................................... 59
1.3.1 ARM Cortex-M4F Processor Core .................................................................................. 59
1.3.2 On-Chip Memory ........................................................................................................... 61
1.3.3 External Peripheral Interface ......................................................................................... 63
1.3.4 Cyclical Redundancy Check (CRC) ............................................................................... 65
1.3.5 Advanced Encryption Standard (AES) Accelerator .......................................................... 65
1.3.6 Data Encryption Standard (DES) Accelerator ................................................................. 66
1.3.7 Secure Hash Algorithm / Message Digest Algorithm (SHA/MD5) ..................................... 66
1.3.8 Serial Communications Peripherals ................................................................................ 67
1.3.9 System Integration ........................................................................................................ 73
1.3.10 Advanced Motion Control ............................................................................................... 79
1.3.11 Analog .......................................................................................................................... 82
1.3.12 JTAG and ARM Serial Wire Debug ................................................................................ 83
1.3.13 Packaging and Temperature .......................................................................................... 84
1.4 TM4C129ENCPDT Microcontroller Hardware Details ...................................................... 84
1.5 Kits .............................................................................................................................. 84
1.6 Support Information ....................................................................................................... 85
2 The Cortex-M4F Processor ................................................................................... 86
2.1 Block Diagram .............................................................................................................. 87
2.2 Overview ...................................................................................................................... 88
2.2.1 System-Level Interface .................................................................................................. 88
2.2.2 Integrated Configurable Debug ...................................................................................... 88
2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 89
2.2.4 Cortex-M4F System Component Details ......................................................................... 89
2.3 Programming Model ...................................................................................................... 90
2.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 90
2.3.2 Stacks .......................................................................................................................... 91
2.3.3 Register Map ................................................................................................................ 91
2.3.4 Register Descriptions .................................................................................................... 93
2.3.5 Exceptions and Interrupts ............................................................................................ 109
2.3.6 Data Types ................................................................................................................. 109
2.4 Memory Model ............................................................................................................ 109
2.4.1 Memory Regions, Types and Attributes ......................................................................... 112
2.4.2 Memory System Ordering of Memory Accesses ............................................................ 113
2.4.3 Behavior of Memory Accesses ..................................................................................... 113
2.4.4 Software Ordering of Memory Accesses ....................................................................... 114
3June 18, 2014
Texas Instruments-Production Data
Tiva
™
TM4C129ENCPDT Microcontroller