Datasheet

The internal system clock (SysClk), is derived from any of the above sources. An internal PLL can
also be used by the PIOSC or MOSC clock to generate the system clock and peripheral clocks.
Table 5-3 on page 238 shows how the various clock sources can be used in a system.
Table 5-3. Clock Source Options
SysClk generation enabled,
RSCLKCFG Bit Encodings
SysClk
generation
capability?
PLL Enabled,
RSCLKCFG Bit
Encodings
Drive PLL
Capability?
Clock Source
USEPLL = 0, OSCSRC = 0x0YesUSEPLL = 1, PLLSRC =
0x0
YesPrecision Internal Oscillator
(PIOSC)
USEPLL = 0, OSCSRC = 0x3YesUSEPLL = 1, PLLSRC =
0x3
YesMain Oscillator (MOSC)
USEPLL = 0, OSCSRC = 0x2Yes-NoLow Frequency Internal Oscillator
(LFIOSC)
a
USEPLL = 0, OSCSRC = 0x4Yes-NoHibernation Module RTC Oscillator
(RTCOSC). 32.768-kHz Oscillator
or HIB LFIOSC
a. LFIOSC frequency is characterized as 33 kHz nominal, 10 kHz minimum and 90 kHz maximum.
5.2.5.2 Clock Configuration
The Run and Sleep Mode Configuration Register (RSCLKCFG) provides control for the system
clock in run and sleep mode. The Deep Sleep Clock Configuration register (DSCLKCFG) specifies
the behavior of the clock system while in deep sleep mode. These registers control the following
clock functionality:
■ Source of system clock in run and sleep mode
■ Source of system clock in deep-sleep mode
■ Enabling/disabling of PLL-derived system clock
■ Clock divisors for PLL or oscillator, depending on what is enabled
■ Enabling of memory timing parameters for flash
Providing further configuration, the PLL Frequency n (PLLFREQn) registers allow the PLL VCO
frequency (f
VCO
) to multiplied or divided by programmable values depending on the system clock
speed required.
Table 5-4 on page 238 shows the state of the clock sources following a Power-On Reset.
Table 5-4. Clock Source State Following POR
Power-On Reset StateClock Source
Disabled/Powered OffPLL
Disabled/Powered OffMOSC
EnabledLFIOSC
EnabledPIOSC
DisabledHIB RTCOSC
Figure 5-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system
clock signal and can be individually enabled/disabled.
June 18, 2014238
Texas Instruments-Production Data
System Control