Datasheet

2. The internal reset is released and the core executes a full initialization of the device. Upon
completion, the core loads from memory the initial stack pointer, the initial program counter,
and the first instruction designated by the program counter, and then begins execution.
The internal POR is only active on the initial power-up of the microcontroller, when the microcontroller
wakes from hibernation, and when the VDD supply drops below the its defined operating limit. Please
refer to the Electrical Characteristics chapter for information on exact values. The Power-On Reset
timing is shown in “Power and Brown-Out” on page 1950.
5.2.2.4 External RST Pin
When the external RST pin is asserted it initiates a system reset or Power-On Reset depending on
what has been configured in the Reset Behavior Control (RESBEHAVCTL) Register. If the EXTRES
bit field in RESBEHAVCTL is set to 0x3 then a simulated full initialization will begin upon RST
assertion. If these bits are programmed to 0x2 then a system reset is issued. When EXTRES is set
to a 0x0 or 0x1, then the external RST pin performs its default operation upon assertion, which is
issuing a full simulated POR.
An external reset pin (RST) that is configured to generate a Power-On Reset resets the microcontroller
including the core and all the on-chip peripherals. The external reset sequence is as follows:
1. The external reset pin (RST) is asserted for the duration specified by T
MIN
and then deasserted
(see “Reset” on page 1955). This generates an internal POR signal.
2. The microcontroller waits for internal POR to go inactive.
3. The internal reset is released and the core executes a full initialization of the device. Upon
completion, the core loads from memory the initial stack pointer, the initial program counter,
and the first instruction designated by the program counter, and then begins execution. Refer
to “Reset” on page 1955 for internal reset deassertion timing.
An external reset pin (RST) that is configured to generate a system reset will reset the microcontroller
including the core and all the on-chip peripherals. The external reset sequence is as follows:
1. The external reset pin (RST) is asserted for the duration specified by T
MIN
and then deasserted
(see “Reset” on page 1955).
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
Note: It is recommended that the trace for the RST signal must be kept as short as possible. Be
sure to place any components connected to the RST signal as close to the microcontroller
as possible.
If the application only uses the internal POR circuit, the RST input must be connected to the power
supply (V
DD
) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 5-1 on page 231.
The RST input has filtering which requires a minimum pulse width in order for the reset pulse to be
recognized, see Table 30-14 on page 1955.
To improve noise immunity and/or to delay reset at power up, the RST input may be connected to
an RC network as shown in Figure 5-2 on page 231. If the application requires the use of an external
reset switch, Figure 5-3 on page 231 shows the proper circuitry to use. In the figures, the R
PU
and
C
1
components define the power-on delay. The external reset timing is shown in Figure
30-11 on page 1956.
June 18, 2014230
Texas Instruments-Production Data
System Control