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Table 23-5. Enhanced Transmit Descriptor 3 (TDES3) ......................................................... 1542

Table 23-6. Enhanced Transmit Descriptor 6 (TDES6) ......................................................... 1542

Table 23-7. Enhanced Transmit Descriptor 7 (TDES7) ......................................................... 1542

Table 23-8. Enhanced Receive Descriptor 0 (RDES0) .......................................................... 1543

Table 23-9. RDES0 Checksum Offload bits ......................................................................... 1545

Table 23-10. Enhanced Receive Descriptor 1 (RDES1) .......................................................... 1546

Table 23-11. Enhanced Receive Descriptor 2 (RDES2) .......................................................... 1546

Table 23-12. Enhanced Receive Descriptor 3 (RDES3) .......................................................... 1546

Table 23-13. Enhanced Received Descriptor 4 (RDES4) ........................................................ 1546

Table 23-14. Enhanced Receive Descriptor 6 (RDES6) .......................................................... 1548

Table 23-15. Enhanced Receive Descriptor 7 (RDES7) .......................................................... 1548

Table 23-16. TX MAC Flow Control ...................................................................................... 1561

Table 23-17. RX MAC Flow Control ...................................................................................... 1561

Table 23-18. VLAN Match Status .......................................................................................... 1574

Table 23-19. CRC Replacement Based on Bit 27 and Bit 24 of TDES0 ................................... 1576

Table 23-20. Forced Mode Configurations ............................................................................. 1582

Table 23-21. Advertised Mode Configurations ....................................................................... 1583

Table 23-22. EMACPC to PHY Register Mapping .................................................................. 1589

Table 23-23. Ethernet Register Map ..................................................................................... 1591

Table 23-24. PPSCTRL Bit Field Values ............................................................................... 1673

Table 24-1. USB Signals (128TQFP) .................................................................................. 1770

Table 24-2. List of Registers ............................................................................................... 1771

Table 25-1. Analog Comparators Signals (128TQFP) ........................................................... 1778

Table 25-2. Internal Reference Voltage and ACREFCTL Field Values ................................... 1780

Table 25-3. Analog Comparator Voltage Reference Characteristics, V

DDA

= 3.3V, EN= 1, and

RNG = 0 .......................................................................................................... 1781

Table 25-4. Analog Comparator Voltage Reference Characteristics, V

DDA

= 3.3V, EN= 1, and

RNG = 1 .......................................................................................................... 1782

Table 25-5. Analog Comparators Register Map ................................................................... 1783

Table 26-1. PWM Signals (128TQFP) ................................................................................. 1796

Table 26-2. PWM Register Map .......................................................................................... 1803

Table 27-1. QEI Signals (128TQFP) ................................................................................... 1874

Table 27-2. QEI Register Map ............................................................................................ 1878

Table 29-1. GPIO Pins With Special Considerations ............................................................ 1896

Table 29-2. Signals by Pin Number ..................................................................................... 1897

Table 29-3. Signals by Signal Name ................................................................................... 1909

Table 29-4. Signals by Function, Except for GPIO ............................................................... 1921

Table 29-5. GPIO Pins and Alternate Functions ................................................................... 1932

Table 29-6. Possible Pin Assignments for Alternate Functions .............................................. 1935

Table 29-7. Connections for Unused Signals (128-Pin TQFP) ............................................... 1940

Table 30-1. Absolute Maximum Ratings .............................................................................. 1942

Table 30-2. ESD Absolute Maximum Ratings ...................................................................... 1942

Table 30-3. Temperature Characteristics ............................................................................. 1943

Table 30-4. 128-pin TQFP Power Dissipation ...................................................................... 1943

Table 30-5. Thermal Characteristics ................................................................................... 1943

Table 30-6. Recommended DC Operating Conditions .......................................................... 1944

Table 30-7. Recommended FAST GPIO Pad Operating Conditions ...................................... 1944

Table 30-8. Recommended Slow GPIO Pad Operating Conditions ........................................ 1945

June 18, 201422

Texas Instruments-Production Data

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