Datasheet

4.3 Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 215. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs.
The current state of the TAP controller depends on the sequence of values captured on TMS at the
rising edge of TCK. The TAP controller determines when the serial shift chains capture new data,
shift data from TDI towards TDO, and update the parallel load registers. The current state of the
TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register
(DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST, operate on data currently in a DR chain and do not capture, shift,
or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction
to ensure that the serial path between TDI and TDO is always connected (see Table 4-3 on page 223
for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 1948 for JTAG timing diagrams.
Depending on the reset source, the effect on the JTAG module varies. The following reset sources
reset the entire JTAG Module:
■ Externally generated Power-On Reset
The following reset sources reset only the JTAG pin configuration:
■ RST pin Power-On Reset
■ Brown-Out Power-On Reset
■ Watchdog Power-On Reset
■ HIB Module Power-On Reset
■ RST pin System Reset
■ Brown-Out System Reset
■ Software System Reset Request (using the SYSRESREQ bit in the APINT register)
■ Software Peripheral Reset
■ Watchdog System Reset
■ HIB Module System Reset
4.3.1 JTAG Interface Pins
The JTAG interface consists of four standard pins: TCK, TMS, TDI, and TDO. These pins and their
associated state after a power-on reset or reset caused by the RST input are given in Table 4-2.
Detailed information on each pin follows.
June 18, 2014216
Texas Instruments-Production Data
JTAG Interface